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Searched refs:XC (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/clang/test/Modules/Inputs/declare-use/
H A Dmodule.map9 module XC {
36 use XC
47 use XC
/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-vtordisp.cpp167 struct XC : virtual XB { struct
168 XC() { printf("XC"); } in XC() argument
383 sizeof(XC)+
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Ddynamic-cast-hint.cpp22 class XC : public virtual A { }; class
23 class X : public XA, public XB, public XC { };
/llvm-project-15.0.7/clang/test/Sema/
H A Dattr-mode-vector-types.c32 typedef _Complex float __attribute__((mode(XC))) __attribute__((vector_size(256))) vec_t12;
H A Dattr-mode.c50 typedef _Complex float c80 __attribute((mode(XC)));
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td326 bits<6> XC;
345 let Inst{60} = XC{5};
493 bits<6> XC;
507 let Inst{53-57} = XC{4-0};
509 let Inst{60} = XC{5};
522 bits<6> XC;
540 let Inst{60} = XC{5};
1282 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1286 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1290 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
[all …]
H A DPPCScheduleP7.td61 // (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
H A DPPCInstrFormats.td1319 bits<6> XC;
1326 let Inst{21-25} = XC{4-0};
1328 let Inst{28} = XC{5};
/llvm-project-15.0.7/llvm/test/MC/COFF/
H A Dglobal_ctors_dtors.ll2 ; target. Mingw uses .ctors, whereas MSVC uses .CRT$XC*.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp143 return emitMemMemImm(DAG, DL, SystemZISD::XC, Chain, Dst, Dst, Bytes); in EmitTargetCodeForMemset()
152 return emitMemMemReg(DAG, DL, SystemZISD::XC, Chain, Dst, Dst, Size); in EmitTargetCodeForMemset()
H A DREADME.txt39 We only use MVC, XC and CLC for constant-length block operations.
H A DSystemZISelLowering.h123 XC, enumerator
H A DSystemZOperators.td416 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
H A DSystemZScheduleZ196.td421 def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "XC$")>;
H A DSystemZScheduleZEC12.td432 def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "XC$")>;
H A DSystemZScheduleZ13.td459 def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "XC$")>;
H A DSystemZScheduleZ16.td464 def : InstRW<[WLat3LSU, LSU2, FXb, Cracked], (instregex "XC$")>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp645 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0); in evaluate() local
646 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1); in evaluate()
654 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0); in evaluate() local
655 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1); in evaluate()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp535 Value *XC = Builder.CreateFMulFMF(X, C, &I); in visitFMul() local
536 return BinaryOperator::CreateFAddFMF(XC, CC1, &I); in visitFMul()
543 Value *XC = Builder.CreateFMulFMF(X, C, &I); in visitFMul() local
544 return BinaryOperator::CreateFSubFMF(CC1, XC, &I); in visitFMul()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h374 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
H A DRISCVISelLowering.cpp1193 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd() argument
1201 if (XC && OldShiftOpcode == ISD::SRL && XC->isOne()) in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
1212 return !XC; in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h770 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd() argument
783 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne()) in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
791 return !XC; in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h777 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1069 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp8862 ConstantFPSDNode *XC = isConstOrConstSplatFP(X, /* AllowUndefs */ true); in simplifyFPBinop() local
8864 bool HasNan = (XC && XC->getValueAPF().isNaN()) || in simplifyFPBinop()
8866 bool HasInf = (XC && XC->getValueAPF().isInfinity()) || in simplifyFPBinop()

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