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/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp428 if (Writes.size() != Reads.size()) in tryEliminateMoveOrSwap()
435 if (Writes.empty() || Writes.size() > 2) in tryEliminateMoveOrSwap()
504 SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
521 Writes.push_back(WR); in collectWrites()
536 Writes.push_back(WR); in collectWrites()
549 if (Writes.size() > 1) { in collectWrites()
553 auto It = std::unique(Writes.begin(), Writes.end()); in collectWrites()
554 Writes.resize(std::distance(Writes.begin(), It)); in collectWrites()
571 SmallVector<WriteRef, 4> Writes; in checkRAWHazards() local
579 for (const WriteRef &WR : Writes) { in checkRAWHazards()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td67 list <SchedWriteRes> Writes = writes;
827 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond.Writes[0-1]>,
828 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond.Writes[0-3]>,
847 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,
848 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,
849 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,
850 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,
851 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,
852 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,
853 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,
[all …]
H A DARMScheduleA9.td1882 list <WriteSequence> Writes = writes;
2110 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2111 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2112 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2113 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2114 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2115 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2116 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2117 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2215 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
H A DARMParallelDSP.cpp344 SmallVector<Instruction*, 8> Writes; in RecordMemoryOps() local
353 Writes.push_back(&I); in RecordMemoryOps()
370 for (auto Write : Writes) { in RecordMemoryOps()
/llvm-project-15.0.7/polly/lib/Transform/
H A DMaximalStaticExpansion.cpp138 SmallPtrSetImpl<MemoryAccess *> &Writes, in isExpandable() argument
141 Writes.insert(S.getValueDef(SAI)); in isExpandable()
150 auto Writes = S.getPHIIncomings(SAI); in isExpandable() local
155 for (auto Write : Writes) { in isExpandable()
215 Writes.insert(MA); in isExpandable()
402 SmallPtrSet<MemoryAccess *, 4> Writes; in expandPhi() local
404 Writes.insert(MA); in expandPhi()
408 mapAccess(Writes, Dependences, ExpandedSAI, false); in expandPhi()
H A DDeLICM.cpp77 isl::union_map Writes, in computeReachingOverwrite() argument
80 return computeReachingWrite(Schedule, Writes, true, InclPrevWrite, in computeReachingOverwrite()
98 isl::union_set Writes, in computeScalarReachingOverwrite() argument
103 auto WritesMap = isl::union_map::from_domain(Writes); in computeScalarReachingOverwrite()
122 isl::set Writes, bool InclPrevWrite, in computeScalarReachingOverwrite() argument
125 isl::space DomSpace = Writes.get_space(); in computeScalarReachingOverwrite()
128 Schedule, isl::union_set(Writes), InclPrevWrite, InclOverwrite); in computeScalarReachingOverwrite()
636 auto Writes = getDomainFor(DefMA); in computeValueUses() local
639 auto WriteScatter = getScatterFor(Writes); in computeValueUses()
651 Writes.get_space().map_from_domain_and_range(ScatterSpace)); in computeValueUses()
H A DZoneAlgo.cpp171 isl::union_map Writes, in computeReachingDefinition() argument
173 return computeReachingWrite(Schedule, Writes, false, InclDef, InclRedef); in computeReachingDefinition()
189 isl::union_set Writes, in computeScalarReachingDefinition() argument
193 isl::union_map Defs = isl::union_map::from_domain(Writes); in computeScalarReachingDefinition()
215 isl::set Writes, bool InclDef, in computeScalarReachingDefinition() argument
217 isl::space DomainSpace = Writes.get_space(); in computeScalarReachingDefinition()
222 Schedule, isl::union_set(Writes), InclDef, InclRedef); in computeScalarReachingDefinition()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp882 IdxVec Writes, Reads; in collectSchedClasses() local
928 if (!SC.Writes.empty()) { in collectSchedClasses()
946 IdxVec Writes; in collectSchedClasses() local
949 Writes, Reads); in collectSchedClasses()
1038 SC.Writes = OperWrites; in addSchedClass()
1117 SC.Writes = SchedClasses[OldSCIdx].Writes; in createInstRWClass()
1264 IdxVec Writes, Reads; in inferFromItinClass() local
1286 IdxVec Writes, Reads; in inferFromInstRWs() local
1900 IdxVec Writes, Reads; in collectProcResources() local
2006 if (!SC.Writes.empty()) in checkCompleteness()
[all …]
H A DCodeGenSchedule.h128 IdxVec Writes; member
148 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
558 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
634 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
H A DSubtargetEmitter.cpp1059 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1073 Writes.clear(); in GenSchedClassTables()
1076 Writes, Reads); in GenSchedClassTables()
1079 if (Writes.empty()) { in GenSchedClassTables()
1085 Writes, Reads); in GenSchedClassTables()
1089 if (Writes.empty()) { in GenSchedClassTables()
1101 for (unsigned W : Writes) { in GenSchedClassTables()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstrAnalysis.cpp22 APInt &Writes) const { in clearsSuperRegisters()
23 Writes.clearAllBits(); in clearsSuperRegisters()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp351 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
368 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
395 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
422 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
446 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
460 ID.Writes.resize(CurrentDef); in populateWrites()
745 if (D.Writes.empty()) { in createInstruction()
754 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
764 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp249 bool Reads, Writes; in weightCalcHelper() local
250 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in weightCalcHelper()
251 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI); in weightCalcHelper()
254 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
H A DMLRegallocEvictAdvisor.cpp720 bool Reads, Writes; in getLIFeatureComponents() local
721 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in getLIFeatureComponents()
726 Ret.R += (Reads && !Writes) * Freq; in getLIFeatureComponents()
727 Ret.W += (!Reads && Writes) * Freq; in getLIFeatureComponents()
728 Ret.RW += (Reads && Writes) * Freq; in getLIFeatureComponents()
734 if (Writes && IsExiting && LIS->isLiveOutOfMBB(LI, MBB)) in getLIFeatureComponents()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopDataPrefetch.cpp240 bool Writes = false; member
258 Writes = isa<StoreInst>(I); in addInstruction()
269 Writes = true; in addInstruction()
412 ConstantInt::get(I32, P.Writes), in runOnLoop()
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h237 SmallVectorImpl<WriteRef> &Writes,
278 bool tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DInstruction.h376 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
377 DependentWrites = Writes; in setDependentWrites()
378 IsReady = !Writes; in setDependentWrites()
448 SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end. member
/llvm-project-15.0.7/polly/lib/Support/
H A DISLTools.cpp302 isl::union_map Writes, bool Reverse, in computeReachingWrite() argument
321 isl::union_map WriteAction = Schedule.apply_domain(Writes); in computeReachingWrite()
354 polly::computeArrayUnused(isl::union_map Schedule, isl::union_map Writes, in computeArrayUnused() argument
359 isl::union_map WriteActions = Schedule.apply_domain(Writes); in computeArrayUnused()
363 Writes.reverse().range_map().apply_range(Schedule); in computeArrayUnused()
367 Schedule, Writes, true, ReadEltInSameInst, !ReadEltInSameInst); in computeArrayUnused()
384 Schedule, Writes, true, IncludeLastRead, IncludeWrite); in computeArrayUnused()
/llvm-project-15.0.7/polly/include/polly/Support/
H A DISLTools.h339 isl::union_map Writes, bool Reverse,
403 isl::union_map Writes, isl::union_map Reads,
/llvm-project-15.0.7/llvm/utils/gn/build/
H A Dwrite_vcsrevision.gni8 # Writes "$foo_REVISION" and "$foo_REPOSITORY" for each foo in names.
/llvm-project-15.0.7/polly/include/polly/
H A DScopBuilder.h653 bool hasNonHoistableBasePtrInScop(MemoryAccess *MA, isl::union_map Writes);
662 isl::set getNonHoistableCtx(MemoryAccess *Access, isl::union_map Writes);
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h91 APInt &Writes) const;
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsARM.td96 // Writes to the GE bits.
103 // Writes to the GE bits.
106 // Writes to the GE bits.
117 // Writes to the GE bits.
137 // Writes to the GE bits.
140 // Writes to the GE bits.
151 // Writes to the GE bits.
154 // Writes to the GE bits.
157 // Writes to the GE bits.
160 // Writes to the GE bits.
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h224 bool Writes; member
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp603 bool Reads, Writes; in SafeInFPUDelaySlot() local
604 std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg()); in SafeInFPUDelaySlot()
606 if (Reads || Writes) in SafeInFPUDelaySlot()

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