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Searched refs:WR (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp127 if (WR.getWriteState() == &WS) in onInstructionExecuted()
128 WR.notifyExecuted(CurrentCycle); in onInstructionExecuted()
365 if (WR.getWriteState() == &WS) in removeRegisterWrite()
366 WR.commit(); in removeRegisterWrite()
520 if (WR.getWriteState()) { in collectWrites()
521 Writes.push_back(WR); in collectWrites()
528 CommittedWrites.push_back(WR); in collectWrites()
535 if (WR.getWriteState()) { in collectWrites()
536 Writes.push_back(WR); in collectWrites()
579 for (const WriteRef &WR : Writes) { in checkRAWHazards() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h295 unsigned getElapsedCyclesFromWriteBack(const WriteRef &WR) const;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp891 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
892 if (!WR->isSubClassOf("WriteRes")) in FindWriteResources()
894 if (AliasDef == WR->getValueAsDef("WriteType") in FindWriteResources()
895 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
897 PrintFatalError(WR->getLoc(), "Resources are defined for both " in FindWriteResources()
901 ResDef = WR; in FindWriteResources()
H A DCodeGenSchedule.cpp1909 for (Record *WR : WRDefs) { in collectProcResources()
1910 Record *ModelDef = WR->getValueAsDef("SchedModel"); in collectProcResources()
1911 addWriteRes(WR, getProcModel(ModelDef).Index); in collectProcResources()
/llvm-project-15.0.7/llvm/lib/Object/
H A DWindowsResource.cpp327 Error WindowsResourceParser::parse(WindowsResource *WR, in parse() argument
329 auto EntryOrErr = WR->getHeadEntry(); in parse()
347 InputFilenames.push_back(std::string(WR->getFileName())); in parse()
356 Entry, InputFilenames[Node->Origin], WR->getFileName())); in parse()
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DSValBuilder.cpp1069 const auto WR = RTy.getBitWidth(); in simplifySymbolCast() local
1073 if (((WT > WR) && (UR || !UT)) || ((WT == WR) && (UT == UR))) in simplifySymbolCast()
/llvm-project-15.0.7/llvm/include/llvm/Object/
H A DWindowsResource.h157 Error parse(WindowsResource *WR, std::vector<std::string> &Duplicates);
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp794 uint16_t WR = W0; in evaluate() local
796 assert(WR == 64 && WP == 8); in evaluate()
798 RegisterCell RC(WR); in evaluate()
H A DHexagonRegisterInfo.td514 (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> {
567 (add (sequence "WR%u", 0, 15))>;
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DMemorySSA.cpp904 UpwardsWalkResult WR = walkToPhiOrClobber(Paths[Paused]); in tryOptimizePhi() local
905 if (WR.IsKnownClobber) in tryOptimizePhi()
906 Clobbers.push_back({WR.Result, Paused}); in tryOptimizePhi()
909 DefChainEnd = WR.Result; in tryOptimizePhi()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1496 def : InstRW<[N2Write_3cyc_1M], (instregex "^WHILE(RW|WR)_PXX_[BHSD]$")>;