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Searched refs:VecLen (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp881 assert(MaskL.size() == VecLen && MaskR.size() == VecLen); in splitMask()
1404 (void)VecLen; in shuffs1()
1457 SmallVector<int,128> MaskL(VecLen), MaskR(VecLen); in shuffs2()
1521 SmallVector<int,256> MaskL(VecLen), MaskR(VecLen); in shuffp2()
1673 if (M < VecLen) { in scalarizeShuffle()
1677 M -= VecLen; in scalarizeShuffle()
1761 int N = VecLen; in contracting()
1781 int N = VecLen; in contracting()
1813 int N = VecLen; in contracting()
1872 int N = VecLen; in expanding()
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H A DHexagonISelLoweringHVX.cpp608 unsigned VecLen = Values.size(); in buildHvxVectorReg() local
615 assert(ElemSize*VecLen == HwLen); in buildHvxVectorReg()
718 if (ExtLen == VecLen || ExtLen == 2*VecLen) { in buildHvxVectorReg()
744 if (ExtLen == VecLen) in buildHvxVectorReg()
918 unsigned VecLen = Values.size(); in buildHvxVectorPred() local
920 assert(VecLen <= HwLen || VecLen == 8*HwLen); in buildHvxVectorPred()
935 if (VecLen <= HwLen) { in buildHvxVectorPred()
939 assert(HwLen % VecLen == 0); in buildHvxVectorPred()
1299 unsigned BitBytes = HwLen / VecLen; in insertHvxSubvectorPred()
1915 assert(HwLen % VecLen == 0); in LowerHvxSelect()
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H A DHexagonVectorCombine.cpp1045 int VecLen = getSizeOf(Hi); in vlalignb() local
1047 return getElementRange(Builder, Lo, Hi, VecLen - IntAmt->getSExtValue(), in vlalignb()
1048 VecLen); in vlalignb()
1052 assert(VecLen == HwLen && "Expecting an exact HVX type"); in vlalignb()
1060 if (VecLen == 4) { in vlalignb()
1066 if (VecLen == 8) { in vlalignb()
1067 Value *Sub = Builder.CreateSub(getConstInt(VecLen), Amt); in vlalignb()
1079 int VecLen = getSizeOf(Lo); in vralignb() local
1085 assert(VecLen == HwLen && "Expecting an exact HVX type"); in vralignb()
1092 if (VecLen == 4) { in vralignb()
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H A DHexagonSubtarget.cpp251 unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements()); in isTypeForHVX() local
252 while (ElemTy.getSizeInBits() * VecLen > 64) { in isTypeForHVX()
253 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX()
256 VecLen /= 2; in isTypeForHVX()
H A DHexagonISelLowering.cpp1121 unsigned VecLen = CV->getNumOperands(); in LowerConstantPool() local
1122 assert(isPowerOf2_32(VecLen) && in LowerConstantPool()
1124 for (unsigned i = 0; i < VecLen; ++i) in LowerConstantPool()
2151 unsigned VecLen = VT.getVectorMinNumElements(); in getPreferredVectorAction() local
2154 if (VecLen == 1 || VT.isScalableVector()) in getPreferredVectorAction()
2169 if (!isPowerOf2_32(VecLen)) in getPreferredVectorAction()
2193 unsigned VecLen = AM.size(); in LowerVECTOR_SHUFFLE() local
2216 if (AM[F] >= int(VecLen)) { in LowerVECTOR_SHUFFLE()
2670 unsigned VecLen = VecTy.getVectorNumElements(); in insertVector() local
2671 unsigned Scale = VecLen / ValTy.getVectorNumElements(); in insertVector()
H A DHexagonISelDAGToDAG.cpp776 unsigned VecLen = ResTy.getSizeInBits(); in SelectVAlign() local
777 if (VecLen == 32) { in SelectVAlign()
807 assert(VecLen == 64); in SelectVAlign()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp18843 unsigned VecLen; in getIntrinsicForHexagonNonClangBuiltin() member
18892 return {F->IntrinsicID, F->VecLen}; in getIntrinsicForHexagonNonClangBuiltin()
18898 unsigned VecLen; in EmitHexagonBuiltinExpr() local
18899 std::tie(ID, VecLen) = getIntrinsicForHexagonNonClangBuiltin(BuiltinID); in EmitHexagonBuiltinExpr()
18973 auto V2Q = [this, VecLen] (llvm::Value *Vec) { in EmitHexagonBuiltinExpr()
18974 Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandvrt_128B in EmitHexagonBuiltinExpr()
18979 auto Q2V = [this, VecLen] (llvm::Value *Pred) { in EmitHexagonBuiltinExpr()
18980 Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandqrt_128B in EmitHexagonBuiltinExpr()