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Searched refs:Vd (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2854 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2890 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2927 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2935 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2946 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2954 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2964 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3192 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3200 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
5253 // Vq, Vd, Vd[0-7], Idx[0-3]
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H A DARMInstrCDE.td313 bits<5> Vd;
315 let Inst{22} = Vd{0};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
374 bits<5> Vd;
378 let Inst{22} = Vd{0};
387 bits<5> Vd;
391 let Inst{22} = Vd{4};
442 bits<5> Vd;
446 let Inst{22} = Vd{0};
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H A DARMInstrFormats.td2234 bits<5> Vd;
2304 bits<5> Vd;
2330 bits<5> Vd;
2345 bits<5> Vd;
2383 bits<5> Vd;
2405 bits<5> Vd;
2437 bits<5> Vd;
2454 bits<5> Vd;
2482 bits<5> Vd;
2503 bits<5> Vd;
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H A DARMInstrVFP.td1798 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1811 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/llvm-project-15.0.7/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h380 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
381 Flags = Vd.kind(); in Variable()
666 Function(Variable *Vd, SExpr *Bd) in Function() argument
668 Vd->setKind(Variable::VK_Fun); in Function()
673 Vd->setKind(Variable::VK_Fun); in Function()
717 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
720 Vd->setKind(Variable::VK_SFun); in SFunction()
721 Vd->Definition = this; in SFunction()
728 Vd->Definition = this; in SFunction()
1859 Let(Variable *Vd, SExpr *Bd) : SExpr(COP_Let), VarDecl(Vd), Body(Bd) { in Let() argument
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/llvm-project-15.0.7/clang/lib/Analysis/
H A DThreadSafety.cpp264 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
296 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
302 void checkBeforeAfter(const ValueDecl* Vd,
1077 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1105 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1121 auto It = BMap.find(Vd); in getBeforeInfoForDecl()
1124 Info = insertAttrExprs(Vd, Analyzer); in getBeforeInfoForDecl()
1141 if (!Vd) in checkBeforeAfter()
1166 if (CycMap.find(Vd) == CycMap.end()) { in checkBeforeAfter()
1167 CycMap.insert(std::make_pair(Vd, true)); in checkBeforeAfter()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4423 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
4425 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
4523 // concat_vectors(Vd, trunc(smin(smax Vm, -128), 127) ~> SQXTN2(Vd, Vn)
4536 // concat_vectors(Vd, trunc(smin(smax Vm, -32768), 32767) ~> SQXTN2(Vd, Vn)
6194 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
6195 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
6196 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
6197 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
6199 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
6200 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
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H A DAArch64InstrFormats.td7641 bits<5> Vd;
7660 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
7662 bits<5> Vd;
11053 bits<5> Vd;
11071 : CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
11073 : CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
11088 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
11091 "{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
11094 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
11097 "{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
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H A DAArch64SchedPredicates.td282 [// MOVI Vd, #0
287 // MOVI Vd, #0, LSL #0
H A DAArch64SchedA64FX.td2337 // [13] "andv $Vd, $Pg, $Zn";
2586 // [96] "eorv $Vd, $Pg, $Zn";
2616 // [107] "faddv $Vd, $Pg, $Zn";
2709 // [135] "fmaxnmv $Vd, $Pg, $Zn";
2712 // [136] "fmaxv $Vd, $Pg, $Zn";
2727 // [141] "fminnmv $Vd, $Pg, $Zn";
2730 // [142] "fminv $Vd, $Pg, $Zn";
2885 // [196] "lasta $Vd, $Pg, $Zn";
2891 // [198] "lastb $Vd, $Pg, $Zn";
3305 // [336] "orv $Vd, $Pg, $Zn";
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H A DAArch64SchedCyclone.td327 // FMOVv2f64ns Vd.2d, #0.0
336 // ORR.16b Vd,Vn,Vn
637 // Vd is read 5 cycles after issuing the vector load.
H A DSVEInstrFormats.td5044 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5045 asm, "\t$Vd, $Pg, $Zn",
5049 bits<5> Vd;
5058 let Inst{4-0} = Vd;
6484 asm, "\t$Vd, $Pg, $Zn",
6488 bits<5> Vd;
6497 let Inst{4-0} = Vd;
7814 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
7815 asm, "\t$Vd, $Pg, $Zn",
7819 bits<5> Vd;
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/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dcde-fp-vec.txt30 # Vector variant, Vd<0> == 1
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1787 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1791 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1792 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1812 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1816 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1817 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
6016 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTD() local
6017 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTD()
6075 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTQ() local
6076 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTQ()
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/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/
H A Dvmcore-i386-minidump.bz21minidump FreeBSD/
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1270 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1271 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1272 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1273 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
H A DHexagonPseudo.td490 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
/llvm-project-15.0.7/llvm/tools/llvm-objdump/
H A DMachODump.cpp10174 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
10175 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()