Lines Matching refs:Vd
264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
367 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
377 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
387 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
408 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
418 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
428 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
438 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
600 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
608 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
628 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
630 "vld1", Dt, "$Vd, $Rn!",
636 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
638 "vld1", Dt, "$Vd, $Rn, $Rm",
645 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
647 "vld1", Dt, "$Vd, $Rn!",
653 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
655 "vld1", Dt, "$Vd, $Rn, $Rm",
673 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
675 "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> {
681 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
683 "vld1", Dt, "$Vd, $Rn!",
689 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
691 "vld1", Dt, "$Vd, $Rn, $Rm",
736 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
738 "$Vd, $Rn", "", []>, Sched<[WriteVLD4]> {
744 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
746 "vld1", Dt, "$Vd, $Rn!",
752 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
754 "vld1", Dt, "$Vd, $Rn, $Rm",
800 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
802 "vld2", Dt, "$Vd, $Rn", "", []> {
829 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
831 "vld2", Dt, "$Vd, $Rn!",
837 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
839 "vld2", Dt, "$Vd, $Rn, $Rm",
883 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
885 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> {
902 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
904 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
942 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
944 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []>,
962 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
964 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
1031 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1033 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1034 "$src = $Vd",
1035 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1043 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1045 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1046 "$src = $Vd",
1047 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1117 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1120 "\\{$Vd[$lane]\\}, $Rn$Rm",
1121 "$src = $Vd, $Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1144 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1146 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1147 "$src1 = $Vd, $src2 = $dst2", []>, Sched<[WriteVLD1]> {
1180 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1183 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1184 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1215 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1219 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> {
1252 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1257 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1289 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1292 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1330 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1334 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1372 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1374 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1375 [(set VecListOneDAllLanes:$Vd,
1396 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1398 "vld1", Dt, "$Vd, $Rn", "",
1399 [(set VecListDPairAllLanes:$Vd,
1422 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1424 "vld1", Dt, "$Vd, $Rn!",
1431 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1433 "vld1", Dt, "$Vd, $Rn, $Rm",
1441 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1443 "vld1", Dt, "$Vd, $Rn!",
1450 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1452 "vld1", Dt, "$Vd, $Rn, $Rm",
1469 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1471 "vld2", Dt, "$Vd, $Rn", "", []> {
1505 (outs VdTy:$Vd, GPR:$wb),
1507 "vld2", Dt, "$Vd, $Rn!",
1514 (outs VdTy:$Vd, GPR:$wb),
1516 "vld2", Dt, "$Vd, $Rn, $Rm",
1546 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1548 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>,
1577 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1579 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1604 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1606 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1635 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1637 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1703 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1704 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST1]> {
1710 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1711 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST2]> {
1730 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1731 "vst1", Dt, "$Vd, $Rn!",
1738 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1740 "vst1", Dt, "$Vd, $Rn, $Rm",
1748 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1749 "vst1", Dt, "$Vd, $Rn!",
1756 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1758 "vst1", Dt, "$Vd, $Rn, $Rm",
1778 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1779 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST3]> {
1786 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1787 "vst1", Dt, "$Vd, $Rn!",
1794 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1796 "vst1", Dt, "$Vd, $Rn, $Rm",
1844 (ins AddrMode:$Rn, VecListFourD:$Vd),
1845 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1853 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1854 "vst1", Dt, "$Vd, $Rn!",
1861 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1863 "vst1", Dt, "$Vd, $Rn, $Rm",
1911 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1912 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1940 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1941 "vst2", Dt, "$Vd, $Rn!",
1948 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1949 "vst2", Dt, "$Vd, $Rn, $Rm",
1957 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1958 "vst2", Dt, "$Vd, $Rn!",
1965 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1967 "vst2", Dt, "$Vd, $Rn, $Rm",
2009 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
2010 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
2028 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
2029 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
2067 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2068 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2087 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2088 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2153 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2154 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2155 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>,
2203 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2204 "\\{$Vd[$lane]\\}, $Rn$Rm",
2206 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2241 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2242 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2280 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2281 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2314 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2316 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2351 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2353 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2385 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2387 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2425 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2427 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2510 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2511 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2512 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2516 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2517 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2518 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2525 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2526 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2527 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2532 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2533 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2534 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2540 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2542 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2547 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2549 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2555 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2557 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2559 // Same as N2VQIntXnp but with Vd as a src register.
2564 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2566 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2567 let Constraints = "$src = $Vd";
2575 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2576 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2577 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2584 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2585 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2586 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2593 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2594 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2595 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2602 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2603 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2604 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2608 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2610 OpcodeStr, Dt, "$Vd, $Vm",
2611 "$src1 = $Vd, $src2 = $Vm", []>;
2614 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2615 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2616 "$src1 = $Vd, $src2 = $Vm", []>;
2623 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2624 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2625 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2627 let TwoOperandAliasConstraint = "$Vn = $Vd";
2636 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2637 OpcodeStr, "$Vd, $Vn, $Vm", "",
2638 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2640 let TwoOperandAliasConstraint = "$Vn = $Vd";
2648 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2649 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2650 [(set (Ty DPR:$Vd),
2654 let TwoOperandAliasConstraint = "$Vn = $Vd";
2660 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2661 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2662 [(set (Ty DPR:$Vd),
2666 let TwoOperandAliasConstraint = "$Vn = $Vd";
2674 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2675 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2676 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2678 let TwoOperandAliasConstraint = "$Vn = $Vd";
2685 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2686 OpcodeStr, "$Vd, $Vn, $Vm", "",
2687 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2689 let TwoOperandAliasConstraint = "$Vn = $Vd";
2696 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2697 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2698 [(set (ResTy QPR:$Vd),
2703 let TwoOperandAliasConstraint = "$Vn = $Vd";
2709 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2710 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2711 [(set (ResTy QPR:$Vd),
2716 let TwoOperandAliasConstraint = "$Vn = $Vd";
2725 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2726 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2727 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2729 let TwoOperandAliasConstraint = "$Vn = $Vd";
2738 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, OpcodeStr, Dt,
2739 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2747 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2748 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2749 [(set (Ty DPR:$Vd),
2759 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2760 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2761 [(set (Ty DPR:$Vd),
2770 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2771 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2772 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2773 let TwoOperandAliasConstraint = "$Vm = $Vd";
2781 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2782 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2783 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2785 let TwoOperandAliasConstraint = "$Vn = $Vd";
2794 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2795 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2799 // Same as N3VQIntnp but with Vd as a src register.
2805 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2807 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2809 let Constraints = "$src = $Vd";
2817 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2818 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2819 [(set (ResTy QPR:$Vd),
2829 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2830 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2831 [(set (ResTy QPR:$Vd),
2841 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2842 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2843 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2844 let TwoOperandAliasConstraint = "$Vm = $Vd";
2853 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2854 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2855 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2862 (outs DPR:$Vd),
2865 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2866 [(set (Ty DPR:$Vd),
2875 (outs DPR:$Vd),
2878 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2879 [(set (Ty DPR:$Vd),
2889 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2890 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2891 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2897 (outs QPR:$Vd),
2900 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2901 [(set (ResTy QPR:$Vd),
2911 (outs QPR:$Vd),
2914 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2915 [(set (ResTy QPR:$Vd),
2926 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2927 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2928 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2934 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2935 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2936 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2945 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2946 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2947 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2953 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2954 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2955 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2963 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2964 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2965 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2971 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2974 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2975 [(set QPR:$Vd,
2983 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2986 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2987 [(set QPR:$Vd,
2999 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3000 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3001 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
3011 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3012 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3013 [(set QPR:$Vd,
3019 (outs QPR:$Vd),
3022 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3023 [(set (ResTy QPR:$Vd),
3032 (outs QPR:$Vd),
3035 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3036 [(set (ResTy QPR:$Vd),
3047 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
3048 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3049 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
3058 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3059 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3060 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3068 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3069 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3070 [(set QPR:$Vd,
3077 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3078 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3079 [(set QPR:$Vd,
3089 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3090 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3091 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3102 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3103 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3104 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3114 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3115 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3116 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3126 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3127 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
3136 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3137 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3138 [(set (ResTy QPR:$Vd),
3146 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3147 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3148 [(set (ResTy QPR:$Vd),
3158 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3159 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3160 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3163 let TwoOperandAliasConstraint = "$Vn = $Vd";
3172 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3173 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3174 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3179 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3180 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3181 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3191 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3192 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3193 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3199 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3200 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3201 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3205 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3210 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3211 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3212 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3217 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3218 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3219 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3228 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3229 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3230 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3238 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3239 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3240 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3245 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3249 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3251 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3252 [(set DPR:$Vd, (Ty (add DPR:$src1,
3257 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3259 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3260 [(set QPR:$Vd, (Ty (add QPR:$src1,
3266 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3270 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3272 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3273 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3277 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3279 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3280 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3289 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3290 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3291 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3296 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3297 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3298 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3319 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3321 [(set DPR:$Vd, (v8i8 (ARMvcmpz (v8i8 DPR:$Vm), fc)))]>;
3323 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3325 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4i16 DPR:$Vm), fc)))]>;
3327 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3329 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2i32 DPR:$Vm), fc)))]>;
3331 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3333 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
3337 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3339 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4f16 DPR:$Vm), fc)))]>,
3346 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3348 [(set QPR:$Vd, (v16i8 (ARMvcmpz (v16i8 QPR:$Vm), fc)))]>;
3350 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3352 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8i16 QPR:$Vm), fc)))]>;
3354 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3356 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3358 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3360 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3364 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3366 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
3377 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
3378 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3379 [(set QPR:$Vd, (ResTy (ARMvcmp (OpTy QPR:$Vn), (OpTy QPR:$Vm), fc)))]> {
3381 let TwoOperandAliasConstraint = "$Vn = $Vd";
3389 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3390 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3391 [(set DPR:$Vd, (ResTy (ARMvcmp (OpTy DPR:$Vn), (OpTy DPR:$Vm), fc)))]> {
3393 let TwoOperandAliasConstraint = "$Vn = $Vd";
4807 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4810 (OpNode (AccumTy RegTy:$Vd),
4815 let Constraints = "$dst = $Vd";
4828 (ins Ty:$Vd, Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
4832 let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
4833 let Constraints = "$dst = $Vd";
4839 (AccumType (OpNode (AccumType Ty:$Vd),
4844 (!cast<Instruction>(NAME) Ty:$Vd, Ty:$Vn, RHS, VectorIndex32:$lane)>;
4861 (ins QPR:$Vd, QPR:$Vn, QPR:$Vm), N3RegFrm, NoItinerary,
4863 [(set (v4i32 QPR:$dst), (OpNode (v4i32 QPR:$Vd),
4867 let Constraints = "$dst = $Vd";
4875 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
4879 let AsmString = !strconcat(Asm, ".", AsmTy, "\t$Vd, $Vn, $Vm$lane");
4881 let Constraints = "$dst = $Vd";
4885 (AccumTy (OpNode (AccumTy RegTy:$Vd),
4890 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4897 (AccumTy (int_arm_neon_usdot (AccumTy RegTy:$Vd),
4902 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4924 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "$src1 = $Vd", pattern>{
4933 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "", pattern> {
4942 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4954 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4969 def v4f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
4972 def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
4977 def v2f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
4980 def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
4990 (outs DPR:$Vd),
4994 (outs QPR:$Vd),
5000 (outs DPR:$Vd),
5004 (outs QPR:$Vd),
5015 (outs DPR:$Vd),
5020 (outs QPR:$Vd),
5027 (outs DPR:$Vd),
5032 (outs QPR:$Vd),
5132 let TwoOperandAliasConstraint = "$Vm = $Vd" in
5134 "$Vd, $Vm, #0", ARMCCeq>;
5152 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5154 "$Vd, $Vm, #0", ARMCCge>;
5156 "$Vd, $Vm, #0", ARMCCle>;
5175 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5177 "$Vd, $Vm, #0", ARMCCgt>;
5179 "$Vd, $Vm, #0", ARMCClt>;
5208 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5209 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5210 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5211 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5212 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5213 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5214 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5215 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5217 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5218 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5219 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5220 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5221 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5222 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5223 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5224 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5232 : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5233 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5237 : N3VCP8Q0<op1, op2, 0, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5238 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5240 // Vd, Vs, Vs[0-15], Idx[0-1]
5242 : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
5244 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5253 // Vq, Vd, Vd[0-7], Idx[0-3]
5255 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5257 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5275 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5276 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5277 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5278 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5279 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5280 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5281 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5282 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5284 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5285 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5286 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5287 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5288 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5289 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5290 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5291 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5344 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5346 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5347 [(set DPR:$Vd,
5353 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5355 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5356 [(set DPR:$Vd,
5362 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5364 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5365 [(set QPR:$Vd,
5371 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5373 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5374 [(set QPR:$Vd,
5381 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5382 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5384 "vbic", "$Vd, $Vn, $Vm", "",
5385 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
5387 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5389 "vbic", "$Vd, $Vn, $Vm", "",
5390 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
5400 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5402 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5403 [(set DPR:$Vd,
5409 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5411 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5412 [(set DPR:$Vd,
5418 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5420 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5421 [(set QPR:$Vd,
5427 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5429 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5430 [(set QPR:$Vd,
5436 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
5438 "vorn", "$Vd, $Vn, $Vm", "",
5439 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
5441 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5443 "vorn", "$Vd, $Vn, $Vm", "",
5444 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
5456 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
5458 "vmvn", "i16", "$Vd, $SIMM", "",
5459 [(set DPR:$Vd, (v4i16 (ARMvmvnImm timm:$SIMM)))]> {
5463 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
5465 "vmvn", "i16", "$Vd, $SIMM", "",
5466 [(set QPR:$Vd, (v8i16 (ARMvmvnImm timm:$SIMM)))]> {
5470 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
5472 "vmvn", "i32", "$Vd, $SIMM", "",
5473 [(set DPR:$Vd, (v2i32 (ARMvmvnImm timm:$SIMM)))]> {
5477 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
5479 "vmvn", "i32", "$Vd, $SIMM", "",
5480 [(set QPR:$Vd, (v4i32 (ARMvmvnImm timm:$SIMM)))]> {
5487 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
5488 "vmvn", "$Vd, $Vm", "",
5489 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
5491 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5492 "vmvn", "$Vd, $Vm", "",
5493 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5514 : PseudoNeonI<(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5516 [(set DPR:$Vd,
5535 def : Pat<(v8i8 (or (and DPR:$Vn, DPR:$Vd),
5536 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5537 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5538 def : Pat<(v4i16 (or (and DPR:$Vn, DPR:$Vd),
5539 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5540 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5541 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
5542 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5543 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5544 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
5545 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5546 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5550 : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5552 [(set QPR:$Vd,
5571 def : Pat<(v16i8 (or (and QPR:$Vn, QPR:$Vd),
5572 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5573 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5574 def : Pat<(v8i16 (or (and QPR:$Vn, QPR:$Vd),
5575 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5576 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5577 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5578 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5579 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5580 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5581 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5582 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5586 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5589 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5592 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5595 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5601 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5603 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5606 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5608 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5614 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5616 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5619 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5621 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
6137 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
6138 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
6139 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
6141 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6142 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
6143 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
6155 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6156 "vneg", "f32", "$Vd, $Vm", "",
6157 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
6159 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6160 "vneg", "f32", "$Vd, $Vm", "",
6161 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
6163 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6164 "vneg", "f16", "$Vd, $Vm", "",
6165 [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>,
6168 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6169 "vneg", "f16", "$Vd, $Vm", "",
6170 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
6207 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
6208 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6211 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
6212 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6218 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6219 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6220 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6221 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6229 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
6231 "vmov", "i8", "$Vd, $SIMM", "",
6232 [(set DPR:$Vd, (v8i8 (ARMvmovImm timm:$SIMM)))]>;
6233 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
6235 "vmov", "i8", "$Vd, $SIMM", "",
6236 [(set QPR:$Vd, (v16i8 (ARMvmovImm timm:$SIMM)))]>;
6238 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
6240 "vmov", "i16", "$Vd, $SIMM", "",
6241 [(set DPR:$Vd, (v4i16 (ARMvmovImm timm:$SIMM)))]> {
6245 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
6247 "vmov", "i16", "$Vd, $SIMM", "",
6248 [(set QPR:$Vd, (v8i16 (ARMvmovImm timm:$SIMM)))]> {
6252 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
6254 "vmov", "i32", "$Vd, $SIMM", "",
6255 [(set DPR:$Vd, (v2i32 (ARMvmovImm timm:$SIMM)))]> {
6259 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
6261 "vmov", "i32", "$Vd, $SIMM", "",
6262 [(set QPR:$Vd, (v4i32 (ARMvmovImm timm:$SIMM)))]> {
6266 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
6268 "vmov", "i64", "$Vd, $SIMM", "",
6269 [(set DPR:$Vd, (v1i64 (ARMvmovImm timm:$SIMM)))]>;
6270 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
6272 "vmov", "i64", "$Vd, $SIMM", "",
6273 [(set QPR:$Vd, (v2i64 (ARMvmovImm timm:$SIMM)))]>;
6275 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
6277 "vmov", "f32", "$Vd, $SIMM", "",
6278 [(set DPR:$Vd, (v2f32 (ARMvmovFPImm timm:$SIMM)))]>;
6279 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
6281 "vmov", "f32", "$Vd, $SIMM", "",
6282 [(set QPR:$Vd, (v4f32 (ARMvmovFPImm timm:$SIMM)))]>;
6294 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6295 (VMOVv8i8 DPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6296 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6297 (VMOVv16i8 QPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6302 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6303 (VMOVv8i8 DPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6304 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6305 (VMOVv16i8 QPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6318 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6319 (V8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6320 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6321 (V16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6322 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6323 (NV8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6324 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6325 (NV16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6347 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
6348 [(set DPR:$Vd, (v2i32 ARMimmAllZerosD))],
6349 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
6351 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
6352 [(set QPR:$Vd, (v4i32 ARMimmAllZerosV))],
6353 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
6660 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6661 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6662 [(set DPR:$Vd, (Ty (ARMvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6666 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6667 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6668 [(set QPR:$Vd, (ResTy (ARMvduplane (OpTy DPR:$Vm),
6957 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
6959 OpcodeStr, Dt, "$Vd, $Vm", "",
6960 [(set DPR:$Vd, (Ty (ARMvrev64 (Ty DPR:$Vm))))]>;
6962 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6964 OpcodeStr, Dt, "$Vd, $Vm", "",
6965 [(set QPR:$Vd, (Ty (ARMvrev64 (Ty QPR:$Vm))))]>;
6990 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
6992 OpcodeStr, Dt, "$Vd, $Vm", "",
6993 [(set DPR:$Vd, (Ty (ARMvrev32 (Ty DPR:$Vm))))]>;
6995 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
6997 OpcodeStr, Dt, "$Vd, $Vm", "",
6998 [(set QPR:$Vd, (Ty (ARMvrev32 (Ty QPR:$Vm))))]>;
7016 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
7018 OpcodeStr, Dt, "$Vd, $Vm", "",
7019 [(set DPR:$Vd, (Ty (ARMvrev16 (Ty DPR:$Vm))))]>;
7021 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
7023 OpcodeStr, Dt, "$Vd, $Vm", "",
7024 [(set QPR:$Vd, (Ty (ARMvrev16 (Ty QPR:$Vm))))]>;
7054 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
7056 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
7058 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
7059 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
7067 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
7069 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
7070 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
7162 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
7164 "vtbl", "8", "$Vd, $Vn, $Vm", "",
7165 [(set DPR:$Vd, (v8i8 (NEONvtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
7169 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
7171 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7173 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
7175 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7177 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
7180 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7190 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
7192 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
7193 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
7197 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
7199 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
7201 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
7204 "vtbx", "8", "$Vd, $Vn, $Vm",
7205 "$orig = $Vd", []>;
7207 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
7209 "vtbx", "8", "$Vd, $Vn, $Vm",
7210 "$orig = $Vd", []>;
8103 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
8104 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8105 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
8106 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8107 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8108 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8109 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8110 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8111 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8112 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8113 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8114 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8115 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8116 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8117 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8118 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8133 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8134 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8135 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8136 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8137 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8138 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8139 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8140 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8979 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8980 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
8981 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8982 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8984 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8985 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
8986 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8987 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
9066 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
9067 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
9068 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
9069 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
9072 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
9073 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9074 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
9075 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9076 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
9077 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9078 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
9079 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9080 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
9081 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9082 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
9083 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9086 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
9087 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9088 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
9089 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9090 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
9091 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9092 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
9093 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9139 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9140 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9141 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9142 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9156 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9158 (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9161 let Constraints = "$dst = $Vd";
9162 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9170 (ins RegTy:$Vd, RegTy:$Vn,
9174 let Constraints = "$dst = $Vd";
9175 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm$lane");
9180 (AccumTy (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9185 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9197 (outs RegTy:$dst), (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9199 [(set (v4f32 QPR:$dst), (int_arm_neon_bfmmla (v4f32 QPR:$Vd),
9202 let Constraints = "$dst = $Vd";
9203 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9211 (outs QPR:$dst), (ins QPR:$Vd, QPR:$Vn, QPR:$Vm),
9212 NoItinerary, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm", "",
9214 (OpNode (v4f32 QPR:$Vd),
9217 let Constraints = "$dst = $Vd";
9226 (ins QPR:$Vd, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
9227 IIC_VMACD, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm$idx", "", []> {
9231 let Constraints = "$dst = $Vd";
9236 (v4f32 (OpNode (v4f32 QPR:$Vd),
9240 (!cast<Instruction>(NAME) QPR:$Vd,
9251 (outs DPR:$Vd), (ins QPR:$Vm),
9252 NoItinerary, "vcvt", "bf16.f32", "$Vd, $Vm", "", []>;