1787   unsigned Vd = fieldFromInstruction(Val, 8, 5);  in DecodeSPRRegListOperand()  local
1791   if (regs == 0 || (Vd + regs) > 32) {  in DecodeSPRRegListOperand()
1792     regs = Vd + regs > 32 ? 32 - Vd : regs;  in DecodeSPRRegListOperand()
1797   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeSPRRegListOperand()
1800     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))  in DecodeSPRRegListOperand()
1812   unsigned Vd = fieldFromInstruction(Val, 8, 5);  in DecodeDPRRegListOperand()  local
1816   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {  in DecodeDPRRegListOperand()
1817     regs = Vd + regs > 32 ? 32 - Vd : regs;  in DecodeDPRRegListOperand()
1823   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeDPRRegListOperand()
1826     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))  in DecodeDPRRegListOperand()
6016   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeVCVTD()  local
6017   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeVCVTD()
6060   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeVCVTD()
6075   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeVCVTQ()  local
6076   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeVCVTQ()
6119   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeVCVTQ()
6132   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeNEONComplexLane64Instruction()  local
6133   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeNEONComplexLane64Instruction()
6145   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))  in DecodeNEONComplexLane64Instruction()
6147   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))  in DecodeNEONComplexLane64Instruction()