| /llvm-project-15.0.7/llvm/unittests/ADT/ |
| H A D | CombinationGeneratorTest.cpp | 30 std::vector<std::vector<int>> Variants; in TEST() local
34 Variants.emplace_back(State); in TEST()
51 std::vector<std::vector<int>> Variants; in TEST() local
55 Variants.emplace_back(State); in TEST()
70 std::vector<std::vector<int>> Variants; in TEST() local
74 Variants.emplace_back(State); in TEST()
95 Variants.emplace_back(State); in TEST()
114 Variants.emplace_back(State); in TEST()
133 Variants.emplace_back(State); in TEST()
152 Variants.emplace_back(State); in TEST()
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 940 std::vector<InstructionTemplate> Variants; in generateInstructionVariants() local
948 Variants.reserve(NumVariants); in generateInstructionVariants()
950 Variants.emplace_back(&Instr); in generateInstructionVariants()
951 Variants.back().setVariableValues(State); in generateInstructionVariants()
953 return Variants.size() >= NumVariants; in generateInstructionVariants()
956 assert(Variants.size() == NumVariants && in generateInstructionVariants()
957 Variants.size() <= MaxConfigsPerOpcode && in generateInstructionVariants()
959 return Variants; in generateInstructionVariants()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 1380 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in mutuallyExclusive() local
1381 if (any_of(Variants, [PredDef](const Record *R) { in mutuallyExclusive()
1417 static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants, in getAllPredicates() argument
1420 for (auto &Variant : Variants) { in getAllPredicates()
1437 std::vector<TransVariant> Variants; in getIntersectingVariants() local
1448 Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0); in getIntersectingVariants()
1465 if (!Variants.empty()) { in getIntersectingVariants()
1480 Variants.emplace_back(VD, AliasRW.Index, AliasProcIdx, 0); in getIntersectingVariants()
1483 Variants.emplace_back(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0); in getIntersectingVariants()
1488 getAllPredicates(Variants, TransVec[TransIdx].ProcIndex); in getIntersectingVariants()
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| H A D | CodeGenDAGPatterns.cpp | 4517 for (const auto &Variants : ChildVariants) in CombineChildVariants() local
4518 if (Variants.empty()) in CombineChildVariants()
4712 std::vector<std::vector<TreePatternNodePtr>> Variants; in GenerateVariantsOf() local
4716 Variants.push_back(std::move(ChildVariants[i + 1])); in GenerateVariantsOf()
4717 Variants.push_back(std::move(ChildVariants[i])); in GenerateVariantsOf()
4721 Variants.push_back(std::move(ChildVariants[i])); in GenerateVariantsOf()
4722 CombineChildVariants(N, Variants, OutVariants, CDP, DepVars); in GenerateVariantsOf()
4744 std::vector<TreePatternNodePtr> Variants; in GenerateVariants() local
4756 if (Variants.size() == 1) // No additional variants for this pattern. in GenerateVariants()
4762 for (unsigned v = 0, e = Variants.size(); v != e; ++v) { in GenerateVariants()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.cpp | 1937 Variants[] = { in schedule() local
1947 for (std::pair<SISchedulerBlockCreatorVariant, SISchedulerBlockSchedulerVariant> v : Variants) { in schedule()
1958 Variants[] = { in schedule() local
1968 for (std::pair<SISchedulerBlockCreatorVariant, SISchedulerBlockSchedulerVariant> v : Variants) { in schedule()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1664 ArrayRef<unsigned> Variants);
3254 static const unsigned Variants[] = { in getAllVariants() local
3260 return makeArrayRef(Variants); in getAllVariants()
3267 return makeArrayRef(Variants); in getMatchedVariants()
3271 return makeArrayRef(Variants); in getMatchedVariants()
3276 return makeArrayRef(Variants); in getMatchedVariants()
3280 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA, in getMatchedVariants() local
3282 return makeArrayRef(Variants); in getMatchedVariants()
3286 static const unsigned Variants[] = {AMDGPUAsmVariants::DPP}; in getMatchedVariants() local
3287 return makeArrayRef(Variants); in getMatchedVariants()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZOperands.td | 551 // Variants of brtarget for use with branch prediction preload.
565 // Variants of brtarget16/32 with an optional additional TLS symbol.
|
| H A D | SystemZInstrFormats.td | 1866 // Variants of instructions with condition mask
|
| /llvm-project-15.0.7/libcxx/include/ |
| H A D | variant | 169 template <class Visitor, class... Variants>
170 constexpr see below visit(Visitor&&, Variants&&...);
172 template <class R, class Visitor, class... Variants>
173 constexpr R visit(Visitor&&, Variants&&...); // since C++20
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA9.td | 2132 // VFP Load/Store Multiple Variants, and NEON VLDn/VSTn support.
2195 // VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a
2253 // Resources for other (non-LDM/VLDM) Variants.
|
| H A D | ARMInstrNEON.td | 5227 // +fp16fml Floating Point Multiplication Variants
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.td | 485 // Variants of the standard calling conventions for shadow call stack.
|
| H A D | AArch64.td | 105 "Enable v8.2 PAN s1e1R and s1e1W Variants",
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | StackMaps.rst | 221 intrinsic's callsite. Variants of the intrinsic with non-void return
|
| H A D | AMDGPUUsage.rst | 14291 Architecture Core ISA ISA Variants and Extensions
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSchedule.td | 399 list<SchedVar> Variants = variants;
|
| H A D | Target.td | 1466 // Variant - AsmParsers can be of multiple different variants. Variants are
1603 // Variant - AsmWriters can be of multiple different variants. Variants are
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| /llvm-project-15.0.7/libcxx/docs/Status/ |
| H A D | Cxx17Issues.csv | 316 "`2901 <https://wg21.link/LWG2901>`__","Variants cannot properly support allocators","Toronto","|Co…
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | arm_neon.td | 1883 // Variants indexing into a 128-bit vector are A64 only.
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 17594 std::array<unsigned, 8> Variants; member
17598 if (Index >= Variants.size()) in getMMAIntrinsic()
17600 return Variants[Index]; in getMMAIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 1948 // Variants for register/immediate permutations of $b and $c
|