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Searched refs:ValueVT (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp169 if (ValueVT.isVector()) in getCopyFromParts()
178 if (ValueVT.isInteger()) { in getCopyFromParts()
251 if (PartEVT == ValueVT) in getCopyFromParts()
392 if (PartEVT == ValueVT) in getCopyFromPartsVector()
415 if (PartEVT == ValueVT) in getCopyFromPartsVector()
482 if (ValueVT.isVector()) in getCopyToParts()
496 if (PartEVT == ValueVT) { in getCopyToParts()
511 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyToParts()
543 if (PartEVT != ValueVT) { in getCopyToParts()
654 if (PartEVT == ValueVT) { in getCopyToPartsVector()
[all …]
H A DLegalizeTypesGeneric.cpp256 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
281 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
466 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
478 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
H A DFunctionLoweringInfo.cpp391 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
392 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
394 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
H A DLegalizeVectorTypes.cpp5937 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
5939 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp82 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
83 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp148 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
149 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
153 ValueVT = MVT::i32; in SelectIndexedLoad()
157 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
169 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
471 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
518 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5915 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
5921 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5924 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5925 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
5958 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
5989 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
6012 MVT ValueVT = Value.getSimpleValueType(); in Select() local
6017 if (!ValueVT.isVector()) in Select()
6020 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6021 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
H A DX86ISelLowering.h1633 MVT PartVT, EVT ValueVT,
H A DX86ISelLowering.cpp2750 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
2751 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
2752 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
2765 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
2767 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
2768 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
2774 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h563 MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp12393 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
12394 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
12406 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
12408 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
12410 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); in splitValueIntoRegisterParts()
12445 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
12447 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
12457 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
12460 EVT ValueEltVT = ValueVT.getVectorElementType(); in joinRegisterPartsIntoValue()
12466 EVT SameEltTypeVT = ValueVT; in joinRegisterPartsIntoValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h566 MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1454 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1455 assert((ValueVT != MVT::i128 || in splitValueIntoRegisterParts()
1459 if (ValueVT == MVT::i128 && NumParts == 1) { in splitValueIntoRegisterParts()
1469 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1470 assert((ValueVT != MVT::i128 || in joinRegisterPartsIntoValue()
1474 if (ValueVT == MVT::i128 && NumParts == 1) in joinRegisterPartsIntoValue()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h896 MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4399 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4400 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
4402 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4415 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4417 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
4419 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4425 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4000 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument