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Searched refs:ValueReg (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h49 unsigned ValueReg, unsigned Address,
55 unsigned ValueReg, unsigned Address,
245 unsigned ValueReg, unsigned Address,
253 unsigned ValueReg, unsigned Address,
H A DSIRegisterInfo.cpp1169 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1170 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1173 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1484 ? ValueReg in buildSpillLoadStore()
1485 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1518 : ValueReg; in buildSpillLoadStore()
1523 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1531 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1543 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1564 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
[all …]
H A DR600InstrInfo.cpp1089 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1091 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1096 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1112 AddrReg, ValueReg) in buildIndirectWrite()
1121 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1123 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1128 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1144 ValueReg, in buildIndirectRead()
H A DSIRegisterInfo.h414 unsigned LoadStoreOp, int Index, Register ValueReg,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1288 Register ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1289 if (ValueReg == 0) in selectStore()
1292 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1298 MIB.addReg(ValueReg); in selectStore()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
191 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
221 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11562 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
11563 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
11565 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
11707 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
11710 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11711 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
11716 .addReg(ValueReg); in EmitPartwordAtomicBinary()
11717 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
11722 .addReg(ValueReg); in EmitPartwordAtomicBinary()