Lines Matching refs:ValueReg
1155 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1169 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1170 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1173 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
1272 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1290 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1484 ? ValueReg in buildSpillLoadStore()
1485 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1517 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1518 : ValueReg; in buildSpillLoadStore()
1523 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1531 MIB.addReg(ValueReg, RegState::Implicit | State); in buildSpillLoadStore()
1543 SubReg = Register(getSubReg(ValueReg, in buildSpillLoadStore()
1564 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1615 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1625 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); in buildSpillLoadStore()