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/llvm-project-15.0.7/clang/test/CXX/special/class.dtor/
H A Dp3-0x.cpp129 struct VX struct
130 { virtual ~VX() {} }; in ~VX() argument
132 struct VY : VX
136 struct TVY : VX
174 struct TVC : VX
/llvm-project-15.0.7/llvm/test/Demangle/
H A Dms-back-references.test95 ?foo11@@YAXV?$Y@VX@NA@@@NA@@V1NB@@@Z
98 ?foo112@@YAXV?$Y@VX@NA@@@NA@@V?$Y@VX@NB@@@NB@@@Z
101 ?foo22@@YAXV?$Y@V?$Y@VX@NA@@@NB@@@NA@@V?$Y@V?$Y@VX@NA@@@NA@@@NB@@@Z
125 ?foo@NA@PR13207@@YAXV?$Y@VX@NA@PR13207@@@12@@Z
131 ?foo@NB@PR13207@@YAXV?$Y@VX@NA@PR13207@@@12@@Z
134 ?bar@NB@PR13207@@YAXV?$Y@VX@NB@PR13207@@@NA@2@@Z
137 ?spam@NB@PR13207@@YAXV?$Y@VX@NA@PR13207@@@NA@2@@Z
143 ?foobarspam@NB@PR13207@@YAXV?$Y@VX@NB@PR13207@@@12@V?$Y@V?$Y@VX@NB@PR13207@@@NB@PR13207@@@NA@2@V412…
146 ?foobarbaz@NB@PR13207@@YAXV?$Y@VX@NB@PR13207@@@12@V?$Y@V?$Y@VX@NB@PR13207@@@NB@PR13207@@@NA@2@V412@…
149 …foobarbazqux@NB@PR13207@@YAXV?$Y@VX@NB@PR13207@@@12@V?$Y@V?$Y@VX@NB@PR13207@@@NB@PR13207@@@NA@2@V4…
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td224 InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
261 InstrItinData <tc_3c8c15d0, /*SLOT23,VX*/
294 InstrItinData <tc_4942646a, /*SLOT23,VX*/
346 InstrItinData <tc_5cdf8c84, /*SLOT23,VX*/
356 InstrItinData <tc_649072c2, /*SLOT23,VX*/
492 InstrItinData <tc_a19b9305, /*SLOT23,VX*/
531 InstrItinData <tc_ac4046bc, /*SLOT23,VX*/
541 InstrItinData <tc_b091f1c6, /*SLOT23,VX*/
572 InstrItinData <tc_c127de3a, /*SLOT23,VX*/
577 InstrItinData <tc_c4edf264, /*SLOT23,VX*/
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfma-combine.ll395 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
411 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
427 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
443 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
459 ; SI-NOFMA: v_sub_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
475 ; SI-NOFMA: v_sub_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
491 ; SI-NOFMA: v_sub_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
507 ; SI-NOFMA: v_sub_f32_e32 [[VS:v[0-9]]], -1.0, [[VX:v[0-9]]]
555 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
571 ; SI-NOFMA: v_add_f32_e32 [[VS:v[0-9]]], 1.0, [[VX:v[0-9]]]
[all …]
H A Dllvm.round.ll11 ; GCN-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
12 ; GCN: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], 1.0, [[VX]]
14 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]]
65 ; GFX89-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]]
67 ; GFX89: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], [[BFI_K]], [[VX]]
H A Dv_cndmask.ll77 ; SIVI-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[X]]
78 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, [[VX]], [[CC]]
111 ; SIVI-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[X]]
112 ; SIVI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, [[VX]], [[CC]]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp1500 case CASE_VFMA_OPCODE_LMULS(MADD, VX): in findCommutedOpIndices()
1501 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX): in findCommutedOpIndices()
1502 case CASE_VFMA_OPCODE_LMULS(MACC, VX): in findCommutedOpIndices()
1503 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX): in findCommutedOpIndices()
1645 case CASE_VFMA_OPCODE_LMULS(MADD, VX): in commuteInstructionImpl()
1646 case CASE_VFMA_OPCODE_LMULS(NMSUB, VX): in commuteInstructionImpl()
1647 case CASE_VFMA_OPCODE_LMULS(MACC, VX): in commuteInstructionImpl()
1648 case CASE_VFMA_OPCODE_LMULS(NMSAC, VX): in commuteInstructionImpl()
1671 CASE_VFMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX) in commuteInstructionImpl()
1672 CASE_VFMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX) in commuteInstructionImpl()
[all …]
H A DRISCVInstrInfoVSDPatterns.td115 def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
230 : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
H A DRISCVInstrInfoVVLPatterns.td369 defm : VPatBinaryVL_XI<vop, instruction_name, "VX",
394 defm : VPatBinaryVL_XI<vop, instruction_name, "VX",
H A DRISCVInstrInfoVPseudos.td3890 defm : VPatBinaryMaskOut<intrinsic, instruction, "VX",
4073 defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX",
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1939 // E-2 VX-Form
1991 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
2005 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
2034 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
2052 /// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
2085 // VX-Form: [PO VRT EO VRB 1 PS XO]
2104 // VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
H A DPPCInstrP10.td22 // (X-Form, VX-Form, etc.)
151 // VX-Form: [ PO VT R VB RC XO ]
368 // VX-Form: [PO VRT RA VRB XO].
375 // VX-Form: [PO VRT RA RB XO].
382 // VX-Form: [ PO BF // VRA VRB XO ]
H A DPPCInstrAltivec.td487 // VX-Form instructions. AltiVec arithmetic ops.
1432 // VX-Form: [PO VRT / UIM VRB XO].
/llvm-project-15.0.7/llvm/lib/Support/
H A DAPInt.cpp2946 APInt VX = (A*X + B)*X + C; in SolveQuadraticEquationWrap() local
2947 APInt VY = VX + TwoA*X + A + B; in SolveQuadraticEquationWrap()
2949 VX.isNegative() != VY.isNegative() || VX.isZero() != VY.isZero(); in SolveQuadraticEquationWrap()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td19 // MicroOp Count/Types: #(B|X|Y|Z|LD|ST|SD|VX|VY|VSD)
23 // down one Z pipe, six SD pipes, four VX pipes and the total latency is
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td548 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
879 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
H A DSystemZScheduleZ13.td1255 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ16.td1318 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ15.td1312 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;
H A DSystemZScheduleZ14.td1276 def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VX$")>;