Home
last modified time | relevance | path

Searched refs:VTSize (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp200 unsigned VTSize = 4; in EmitTargetCodeForMemcpy() local
238 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
239 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
259 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
266 SrcOff += VTSize; in EmitTargetCodeForMemcpy()
267 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
276 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
282 DstOff += VTSize; in EmitTargetCodeForMemcpy()
283 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
H A DARMCallLowering.cpp76 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); in isSupportedType() local
78 if (VTSize == 64) in isSupportedType()
82 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32; in isSupportedType()
H A DARMISelLowering.cpp8144 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle() local
8145 if (SrcVTSize == VTSize) in ReconstructShuffle()
8151 unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits(); in ReconstructShuffle()
8154 if (SrcVTSize < VTSize) { in ReconstructShuffle()
8155 if (2 * SrcVTSize != VTSize) in ReconstructShuffle()
8165 if (SrcVTSize != 2 * VTSize) in ReconstructShuffle()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1006 unsigned VTSize = VT.getScalarSizeInBits(); in earlyExpandDIVFIX() local
1034 assert(SatW <= VTSize && in earlyExpandDIVFIX()
3750 unsigned VTSize = VT.getScalarSizeInBits(); in ExpandIntRes_MULFIX() local
3771 APInt MinVal = APInt::getSignedMinValue(VTSize); in ExpandIntRes_MULFIX()
3772 APInt MaxVal = APInt::getSignedMaxValue(VTSize); in ExpandIntRes_MULFIX()
3785 APInt MaxVal = APInt::getMaxValue(VTSize); in ExpandIntRes_MULFIX()
3852 if (Scale == VTSize) in ExpandIntRes_MULFIX()
3886 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
3906 unsigned OverflowBits = VTSize - Scale + 1; in ExpandIntRes_MULFIX()
3938 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
[all …]
H A DTargetLowering.cpp231 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering() local
232 while (VTSize > Size) { in findOptimalMemOpLowering()
269 VTSize = Size; in findOptimalMemOpLowering()
272 VTSize = NewVTSize; in findOptimalMemOpLowering()
280 Size -= VTSize; in findOptimalMemOpLowering()
8999 unsigned VTSize = VT.getScalarSizeInBits(); in expandFixedPointMul() local
9029 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
9035 assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && in expandFixedPointMul()
9058 if (Scale == VTSize) in expandFixedPointMul()
9079 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
[all …]
H A DSelectionDAG.cpp6832 if (VTSize > Size) { in getMemcpyLoadsAndStores()
6836 SrcOff -= VTSize - Size; in getMemcpyLoadsAndStores()
6837 DstOff -= VTSize - Size; in getMemcpyLoadsAndStores()
6897 SrcOff += VTSize; in getMemcpyLoadsAndStores()
6898 DstOff += VTSize; in getMemcpyLoadsAndStores()
6899 Size -= VTSize; in getMemcpyLoadsAndStores()
7025 SrcOff += VTSize; in getMemmoveLoadsAndStores()
7039 DstOff += VTSize; in getMemmoveLoadsAndStores()
7124 if (VTSize > Size) { in getMemsetStores()
7128 DstOff -= VTSize - Size; in getMemsetStores()
[all …]
H A DDAGCombiner.cpp17744 TypeSize VTSize = VT.getSizeInBits(); in TransformFPLoadStorePair() local
17748 if (VTSize.isScalable()) in TransformFPLoadStorePair()
17752 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedSize()); in TransformFPLoadStorePair()
20282 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle() local
20292 if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { in createBuildVecShuffle()
20295 unsigned NumConcats = VTSize / InVT1Size; in createBuildVecShuffle()
20302 } else if (InVT1Size == VTSize * 2) { in createBuildVecShuffle()
20338 } else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { in createBuildVecShuffle()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3758 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT() local
3760 if (VTSize < InVTSize) { in LowerVectorFP_TO_INT()
3775 if (VTSize > InVTSize) { in LowerVectorFP_TO_INT()
3994 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP() local
3996 if (VTSize < InVTSize) { in LowerVectorINT_TO_FP()
4011 if (VTSize > InVTSize) { in LowerVectorINT_TO_FP()
9082 if (VTSize == 16) in getRegForInlineAsmConstraint()
9084 if (VTSize == 32) in getRegForInlineAsmConstraint()
9086 if (VTSize == 64) in getRegForInlineAsmConstraint()
9088 if (VTSize == 128) in getRegForInlineAsmConstraint()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp5558 uint64_t VTSize = DL.getTypeStoreSizeInBits(FixedVectorType::get(EltTy, N)); in canMapToVector() local
5559 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || VTSize != DL.getTypeStoreSizeInBits(T)) in canMapToVector()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20835 unsigned VTSize = VT.getSizeInBits(); in lowerFPToIntToFP() local
20838 MVT VecVT = MVT::getVectorVT(VT, 128 / VTSize); in lowerFPToIntToFP()
20844 IntSize != VTSize ? X86ISD::CVTSI2P : (unsigned)ISD::SINT_TO_FP; in lowerFPToIntToFP()