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Searched refs:VT1 (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/unittests/Transforms/IPO/
H A DWholeProgramDevirt.cpp17 VTableBits VT1; in TEST() local
18 VT1.ObjectSize = 8; in TEST()
19 VT1.Before.BytesUsed = {1 << 0}; in TEST()
20 VT1.After.BytesUsed = {1 << 1}; in TEST()
27 TypeMemberInfo TM1{&VT1, 0}; in TEST()
55 VT1.After.BytesUsed = {0xff, 0, 0, 0, 0xff}; in TEST()
62 VTableBits VT1; in TEST() local
63 VT1.ObjectSize = 8; in TEST()
68 TypeMemberInfo TM1{&VT1, 0}; in TEST()
118 VT1.Before.BytesUsed); in TEST()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/WholeProgramDevirt/
H A Dimport.ll33 ; VCP: [[VT1:%.*]] = bitcast {{.*}} to i8*
37 …; VCP-X86: [[GEP1:%.*]] = getelementptr i8, i8* [[VT1]], i32 ptrtoint ([0 x i8]* @__typeid_typeid1…
38 ; VCP-ARM: [[GEP1:%.*]] = getelementptr i8, i8* [[VT1]], i32 42
42 ; BRANCH-FUNNEL-NOVCP: [[VT1:%.*]] = bitcast {{.*}} to i8*
43 …d ()* @__typeid_typeid1_0_branch_funnel to i32 (i8*, i8*, i32)*)(i8* nest [[VT1]], i8* %obj, i32 1)
52 ; BRANCH-FUNNEL: [[VT1:%.*]] = bitcast {{.*}} to i8*
66 …d ()* @__typeid_typeid2_8_branch_funnel to i1 (i8*, i8*, i32)*)(i8* nest [[VT1]], i8* %obj, i32 un…
H A Dvirtual-const-prop-end.ll70 ; CHECK: [[VT1:%[^ ]*]] = bitcast [3 x i8*]* {{.*}} to i8*
77 ; CHECK: [[VTGEP1:%[^ ]*]] = getelementptr i8, i8* [[VT1]], i32 24
H A Dvirtual-const-prop-begin.ll75 ; CHECK: [[VT1:%[^ ]*]] = bitcast [3 x i8*]* {{.*}} to i8*
82 ; CHECK: [[VTGEP1:%[^ ]*]] = getelementptr i8, i8* [[VT1]], i32 -1
H A Dbranch-funnel.ll110 ; RETP: [[VT1:%.*]] = bitcast {{.*}} to i8*
111 …...)* @__typeid_typeid1_0_branch_funnel to i32 (i8*, i8*, i32)*)(i8* nest [[VT1]], i8* %obj, i32 1)
H A Dvirtual-const-prop-check.ll105 ; CHECK: [[VT1:%[^ ]*]] = bitcast [3 x i8*]* {{.*}} to i8*
110 ; CHECK: [[VTGEP1:%[^ ]*]] = getelementptr i8, i8* [[VT1]], i32 -1
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h89 static int ValCompare(const PassNameParser::OptionInfo *VT1, in ValCompare() argument
91 return VT1->Name.compare(VT2->Name); in ValCompare()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h141 bool isTruncateFree(EVT VT1, EVT VT2) const override;
145 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DBPFISelLowering.cpp200 bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
201 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
203 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
216 bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
217 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
219 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1400 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
1401 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1404 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
1412 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
1414 return false && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h618 SDVTList getVTList(EVT VT1, EVT VT2);
619 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
620 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1585 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1586 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1588 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1590 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1620 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1622 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1624 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
[all …]
H A DTargetLowering.h1526 EVT VT1; in getRegisterType() local
1529 (void)getVectorTypeBreakdown(Context, VT, VT1, in getRegisterType()
1559 EVT VT1; variable
1562 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dattr-mode-tmpl.cpp28 …typedef T __attribute__((mode(V2SI))) VT1; // expected-error{{mode attribute only supported for in… in CheckPrimitiveTypes() typedef
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1266 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1279 bool isZExtFree(EVT VT1, EVT VT2) const override;
1299 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9221 ID.AddInteger(VT1.getRawBits()); in getVTList()
9228 Array[0] = VT1; in getVTList()
9239 ID.AddInteger(VT1.getRawBits()); in getVTList()
9247 Array[0] = VT1; in getVTList()
9259 ID.AddInteger(VT1.getRawBits()); in getVTList()
9268 Array[0] = VT1; in getVTList()
9481 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
9487 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
9501 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
9689 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transforms.mlir339 // CHECK: %[[VT1:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C2]]], {{.*}} : memref<4…
347 // CHECK: %[[CMP1:.*]] = arith.cmpf ult, %[[VT1]], %[[VT5]] : vector<2x2xf32>
351 // CHECK: %[[VT1:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C2]]], {{.*}} : memref<4…
359 // CHECK: %[[SEL1:.*]] = arith.select %[[CMP1]], %[[VT1]], %[[VT5]] : vector<2x2xi1>, vecto…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfma-combine.ll591 ; SI-NOFMA: v_sub_f32_e32 [[VT1:v[0-9]]], 1.0, [[VT:v[0-9]]]
592 ; SI-NOFMA: v_mul_f32_e32 [[VTY:v[0-9]]], [[VY:v[0-9]]], [[VT1]]
613 ; SI-NOFMA: v_add_f64 [[VT1:v\[[0-9]+:[0-9]+\]]], -[[VT:v\[[0-9]+:[0-9]+\]]], 1.0
614 ; SI-NOFMA: v_mul_f64 [[VTY:v\[[0-9]+:[0-9]+\]]], [[VY:v\[[0-9]+:[0-9]+\]]], [[VT1]]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h594 bool isTruncateFree(EVT VT1, EVT VT2) const override;
599 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DAArch64ISelLowering.cpp3604 EVT VT1 = Op.getValue(1).getValueType(); in lowerADDSUBCARRY() local
3615 SDVTList VTs = DAG.getVTList(VT0, VT1); in lowerADDSUBCARRY()
3621 IsSigned ? overflowFlagToValue(Sum.getValue(1), VT1, DAG) in lowerADDSUBCARRY()
12573 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
12575 uint64_t NumBits1 = VT1.getFixedSizeInBits(); in isTruncateFree()
12617 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
12619 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
12625 EVT VT1 = Val.getValueType(); in isZExtFree() local
12626 if (isZExtFree(VT1, VT2)) { in isZExtFree()
12634 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() && in isZExtFree()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h174 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp181 EVT VT1 = Val.getValueType(); in isZExtFree() local
182 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
186 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h130 bool isTruncateFree(EVT VT1, EVT VT2) const override;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp76 for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1020 bool isTruncateFree(EVT VT1, EVT VT2) const override;

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