Home
last modified time | relevance | path

Searched refs:VRC (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp60 VRC = RC; in Initialize()
163 VRC, MRI, TII); in GetValueInMiddleOfBlock()
201 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
305 Updater->VRC, Updater->MRI, in GetUndefVal()
316 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrVec.td559 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
561 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
571 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
666 (ins VRC:$vy, VRC:$vz, VRC:$vw)>;
669 (ins VRC:$vy, RC:$sy, VRC:$vw)>;
672 (ins VRC:$vy, SIMM:$sy, VRC:$vw)>;
675 (ins RC:$sy, VRC:$vz, VRC:$vw)>;
678 (ins SIMM:$sy, VRC:$vz, VRC:$vw)>;
715 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>;
726 (ins VRC:$vy, VRC:$vz, RC:$sy)>;
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineSSAUpdater.h44 const TargetRegisterClass *VRC; variable
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp4866 if (RI.getCommonSubClass(VRC64, VRC)) in legalizeOpWithMove()
4867 VRC = VRC64; in legalizeOpWithMove()
4869 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
4871 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
5275 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
5276 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
5753 VRC = OpRC; in legalizeOperands()
5763 if (!VRC) { in legalizeOperands()
5766 VRC = &AMDGPU::VReg_1RegClass; in legalizeOperands()
5776 RC = VRC; in legalizeOperands()
[all …]
H A DSIRegisterInfo.h248 getEquivalentSGPRClass(const TargetRegisterClass *VRC) const;
H A DSIRegisterInfo.cpp2684 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass() local
2685 assert(VRC && "Invalid register class size"); in getEquivalentVGPRClass()
2686 return VRC; in getEquivalentVGPRClass()
2698 SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
2699 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td160 class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
162 width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1),
231 class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
233 0b000, (outs), (ins VRC:$vs3, GPR:$rs1),
814 multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
819 def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
823 multiclass VWholeLoadEEW64<bits<3> nf, string opcodestr, RegisterClass VRC, SchedReadWrite schedrw>…
824 def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v", VRC>,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp452 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
453 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
457 if (RC && RC != VRC) in ConstrainForSubReg()