4864   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);  in legalizeOpWithMove()  local
4866   if (RI.getCommonSubClass(VRC64, VRC))  in legalizeOpWithMove()
4867     VRC = VRC64;  in legalizeOpWithMove()
4869     VRC = &AMDGPU::VGPR_32RegClass;  in legalizeOpWithMove()
4871   Register Reg = MRI.createVirtualRegister(VRC);  in legalizeOpWithMove()
5270   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);  in readlaneVGPRToSGPR()  local
5271   const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);  in readlaneVGPRToSGPR()
5273   unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;  in readlaneVGPRToSGPR()
5275   if (RI.hasAGPRs(VRC)) {  in readlaneVGPRToSGPR()
5276     VRC = RI.getEquivalentVGPRClass(VRC);  in readlaneVGPRToSGPR()
5277     Register NewSrcReg = MRI.createVirtualRegister(VRC);  in readlaneVGPRToSGPR()
5746     const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;  in legalizeOperands()  local
5753         VRC = OpRC;  in legalizeOperands()
5762     if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {  in legalizeOperands()
5763       if (!VRC) {  in legalizeOperands()
5766           VRC = &AMDGPU::VReg_1RegClass;  in legalizeOperands()
5768           VRC = RI.isAGPRClass(getOpRegClass(MI, 0))  in legalizeOperands()
5772         VRC = RI.isAGPRClass(getOpRegClass(MI, 0))  in legalizeOperands()
5773                   ? RI.getEquivalentAGPRClass(VRC)  in legalizeOperands()
5774                   : RI.getEquivalentVGPRClass(VRC);  in legalizeOperands()
5776       RC = VRC;  in legalizeOperands()
5813         const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);  in legalizeOperands()  local
5814         if (VRC == OpRC)  in legalizeOperands()
5817         legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc());  in legalizeOperands()