| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | MVEVPTBlockPass.cpp | 75 if (CmpMI->modifiesRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
77 if (CmpMI->readsRegister(ARM::VPR, TRI)) in findVCMPToFoldIntoVPST()
135 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR)) in IsVPRDefinedOrKilledByBlock()
|
| H A D | MVETPAndVPTOptimisationsPass.cpp | 931 Register VPR = Instr.getOperand(PIdx + 1).getReg(); in ReplaceConstByVPNOTs() local
932 if (!VPR.isVirtual()) in ReplaceConstByVPNOTs()
936 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs()
960 if (LastVPTReg != 0 && LastVPTReg != VPR && LastVPTImm == Imm) { in ReplaceConstByVPNOTs()
962 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
979 if (MRI->use_empty(VPR)) { in ReplaceConstByVPNOTs()
986 VPR = NewVPR; in ReplaceConstByVPNOTs()
990 LastVPTReg = VPR; in ReplaceConstByVPNOTs()
|
| H A D | ARMLowOverheadLoops.cpp | 86 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
90 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
94 return MI.findRegisterUseOperandIdx(ARM::VPR) != -1; in hasVPRUse()
199 assert((CurrentPredicates.size() || MI->getParent()->isLiveIn(ARM::VPR)) in CreateVPTBlock()
1035 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1247 if (!MO.isReg() || !MO.isUse() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
1689 MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR); in ConvertVPTBlocks()
|
| H A D | ARMRegisterInfo.td | 203 // on the instruction they are used in and for VPR 32 was chosen such that it
205 def VPR : ARMReg<32, "vpr">;
400 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
458 // Scalar single and double precision floating point and VPR register class,
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
|
| H A D | ARMInstrVFP.td | 326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
2520 // System level VPR/P0 -> GPR
2521 let Uses = [VPR] in
2591 // System level GPR -> VPR/P0
2592 let Defs = [VPR] in
2880 let Uses = [VPR] in {
2886 let Defs = [VPR] in {
|
| H A D | ARMExpandPseudoInsts.cpp | 1314 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1325 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1405 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1499 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1683 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
|
| H A D | ARMBaseInstrInfo.cpp | 878 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
987 } else if (DestReg == ARM::VPR) { in copyPhysReg()
993 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
|
| H A D | ARMInstrMVE.td | 4478 // example when moving between rGPR and VPR.P0 as part of predicate vector
6606 let Defs = [VPR];
6718 let Defs = [VPR];
6765 let Uses = [VPR];
|
| H A D | ARMInstrFormats.td | 226 // always either zero_reg or VPR, but needs to be modelled as an
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-aapcs.ll | 115 ; Check if VPR can be correctly pass by stack.
|
| /llvm-project-15.0.7/llvm/include/llvm/ProfileData/ |
| H A D | InstrProfData.inc | 457 getValueProfRecordNext(ValueProfRecord *VPR);
459 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /llvm-project-15.0.7/compiler-rt/include/profile/ |
| H A D | InstrProfData.inc | 457 getValueProfRecordNext(ValueProfRecord *VPR);
459 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 6248 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6269 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6462 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6936 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6973 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6984 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6985 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-vpt-optimisations.mir | 648 ; VCCR/VPR is written to in-between.
1001 ; that writes to VPR, and that doesn't use any of the registers we care about.
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3729 if (Regs.back().second == ARM::VPR) in CreateRegList()
3735 if (Regs.back().second == ARM::VPR) in CreateRegList()
4583 if (Reg == ARM::VPR && in parseRegisterList()
|