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Searched refs:VECREDUCE_XOR (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-reductions.ll172 ; CHECK: [[VECREDUCE_XOR:%[0-9]+]]:_(s32) = G_VECREDUCE_XOR [[COPY]](<4 x s32>)
173 ; CHECK: $w0 = COPY [[VECREDUCE_XOR]](s32)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1284 VECREDUCE_XOR, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp434 case ISD::VECREDUCE_XOR: in LegalizeOp()
890 case ISD::VECREDUCE_XOR: in Expand()
H A DSelectionDAGDumper.cpp482 case ISD::VECREDUCE_XOR: return "vecreduce_xor"; in getOperationName()
H A DLegalizeIntegerTypes.cpp238 case ISD::VECREDUCE_XOR: in PromoteIntegerResult()
1709 case ISD::VECREDUCE_XOR: in PromoteIntegerOperand()
2232 case ISD::VECREDUCE_XOR: in getExtendForIntVecReduction()
2277 if (Opcode == ISD::VECREDUCE_XOR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2278 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_XOR, InVT) && in PromoteIntOp_VECREDUCE()
2542 case ISD::VECREDUCE_XOR: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp689 case ISD::VECREDUCE_XOR: in ScalarizeVectorOperand()
2763 case ISD::VECREDUCE_XOR: in SplitVectorOperand()
5479 case ISD::VECREDUCE_XOR: in WidenVectorOperand()
H A DLegalizeDAG.cpp1191 case ISD::VECREDUCE_XOR: in LegalizeOp()
3831 case ISD::VECREDUCE_XOR: in ExpandNode()
H A DSelectionDAG.cpp393 case ISD::VECREDUCE_XOR: in getVecReduceBaseOpcode()
5390 return getNode(ISD::VECREDUCE_XOR, DL, VT, Operand); in getNode()
H A DSelectionDAGBuilder.cpp9582 Res = DAG.getNode(ISD::VECREDUCE_XOR, dl, VT, Op1); in visitVectorReduce()
H A DDAGCombiner.cpp1805 case ISD::VECREDUCE_XOR: in visit()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp463 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
507 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
781 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
3431 case ISD::VECREDUCE_XOR: in LowerOperation()
5132 case ISD::VECREDUCE_XOR: in getRVVReductionOp()
5145 Op.getOpcode() == ISD::VECREDUCE_XOR || in lowerVectorMaskVecReduction()
5194 case ISD::VECREDUCE_XOR: in lowerVectorMaskVecReduction()
7381 case ISD::VECREDUCE_XOR: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp864 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1183 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1229 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1422 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in AArch64TargetLowering()
1708 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in addTypeForFixedLengthSVE()
5543 case ISD::VECREDUCE_XOR: in LowerOperation()
12172 Op.getOpcode() == ISD::VECREDUCE_XOR || in LowerVECREDUCE()
12198 case ISD::VECREDUCE_XOR: in LowerVECREDUCE()
21444 case ISD::VECREDUCE_XOR: { in LowerPredReductionToSVE()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp340 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp301 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); in addMVEVectorTypes()
10145 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break; in LowerVecReduce()
10428 case ISD::VECREDUCE_XOR: in LowerOperation()