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Searched refs:VECREDUCE_OR (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-reductions.ll158 ; CHECK: [[VECREDUCE_OR:%[0-9]+]]:_(s32) = G_VECREDUCE_OR [[COPY]](<4 x s32>)
159 ; CHECK: $w0 = COPY [[VECREDUCE_OR]](s32)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1283 VECREDUCE_OR, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp433 case ISD::VECREDUCE_OR: in LegalizeOp()
889 case ISD::VECREDUCE_OR: in Expand()
H A DSelectionDAGDumper.cpp481 case ISD::VECREDUCE_OR: return "vecreduce_or"; in getOperationName()
H A DLegalizeIntegerTypes.cpp237 case ISD::VECREDUCE_OR: in PromoteIntegerResult()
1708 case ISD::VECREDUCE_OR: in PromoteIntegerOperand()
2231 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
2284 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2285 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) && in PromoteIntOp_VECREDUCE()
2541 case ISD::VECREDUCE_OR: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp688 case ISD::VECREDUCE_OR: in ScalarizeVectorOperand()
2762 case ISD::VECREDUCE_OR: in SplitVectorOperand()
5478 case ISD::VECREDUCE_OR: in WidenVectorOperand()
H A DLegalizeDAG.cpp1190 case ISD::VECREDUCE_OR: in LegalizeOp()
3830 case ISD::VECREDUCE_OR: in ExpandNode()
H A DSelectionDAG.cpp390 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
5395 return getNode(ISD::VECREDUCE_OR, DL, VT, Operand); in getNode()
H A DDAGCombiner.cpp1804 case ISD::VECREDUCE_OR: in visit()
23341 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
23356 if ((Opcode == ISD::VECREDUCE_OR && in visitVECREDUCE()
H A DSelectionDAGBuilder.cpp9579 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); in visitVectorReduce()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp462 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
507 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
781 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
3430 case ISD::VECREDUCE_OR: in LowerOperation()
5130 case ISD::VECREDUCE_OR: in getRVVReductionOp()
5144 Op.getOpcode() == ISD::VECREDUCE_OR || in lowerVectorMaskVecReduction()
5187 case ISD::VECREDUCE_OR: in lowerVectorMaskVecReduction()
7380 case ISD::VECREDUCE_OR: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp863 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1182 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1228 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1421 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1702 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addTypeForFixedLengthSVE()
5542 case ISD::VECREDUCE_OR: in LowerOperation()
12171 Op.getOpcode() == ISD::VECREDUCE_OR || in LowerVECREDUCE()
12188 case ISD::VECREDUCE_OR: in LowerVECREDUCE()
18407 LHS = DAG.getNode(ISD::VECREDUCE_OR, DL, MVT::i1, LHS->getOperand(0)); in performSETCCCombine()
21433 case ISD::VECREDUCE_OR: in LowerPredReductionToSVE()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp340 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp300 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addMVEVectorTypes()
10144 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in LowerVecReduce()
10427 case ISD::VECREDUCE_OR: in LowerOperation()