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Searched refs:VECREDUCE_FMAX (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-reductions.ll76 ; CHECK: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[BITCAST]](<4 x s32>)
77 ; CHECK: $s0 = COPY [[VECREDUCE_FMAX]](s32)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1275 VECREDUCE_FMAX, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp441 case ISD::VECREDUCE_FMAX: in LegalizeOp()
897 case ISD::VECREDUCE_FMAX: in Expand()
H A DSelectionDAGDumper.cpp487 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax"; in getOperationName()
H A DLegalizeFloatTypes.cpp144 case ISD::VECREDUCE_FMAX: in SoftenFloatResult()
2305 case ISD::VECREDUCE_FMAX: in PromoteFloatResult()
2668 case ISD::VECREDUCE_FMAX: in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp694 case ISD::VECREDUCE_FMAX: in ScalarizeVectorOperand()
2768 case ISD::VECREDUCE_FMAX: in SplitVectorOperand()
5484 case ISD::VECREDUCE_FMAX: in WidenVectorOperand()
H A DLegalizeDAG.cpp1196 case ISD::VECREDUCE_FMAX: in LegalizeOp()
3836 case ISD::VECREDUCE_FMAX: in ExpandNode()
H A DSelectionDAG.cpp408 case ISD::VECREDUCE_FMAX: in getVecReduceBaseOpcode()
H A DSelectionDAGBuilder.cpp9597 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); in visitVectorReduce()
H A DDAGCombiner.cpp1810 case ISD::VECREDUCE_FMAX: in visit()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp865 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp468 ISD::VECREDUCE_FMAX}; in RISCVTargetLowering()
684 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in RISCVTargetLowering()
3438 case ISD::VECREDUCE_FMAX: in LowerOperation()
5295 case ISD::VECREDUCE_FMAX: in getRVVFPReductionOpAndOperands()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1058 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
1318 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
1700 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addTypeForFixedLengthSVE()
5549 case ISD::VECREDUCE_FMAX: in LowerOperation()
12202 case ISD::VECREDUCE_FMAX: in LowerVECREDUCE()
12224 case ISD::VECREDUCE_FMAX: { in LowerVECREDUCE()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addMVEVectorTypes()
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom); in addMVEVectorTypes()
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom); in addMVEVectorTypes()
10146 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
10433 case ISD::VECREDUCE_FMAX: in LowerOperation()