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Searched refs:VECREDUCE_FADD (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-reduce-fadd.mir14 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>)
15 ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32)
33 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s64) = G_VECREDUCE_FADD [[COPY]](<2 x s64>)
34 ; CHECK: $x0 = COPY [[VECREDUCE_FADD]](s64)
59 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s64) = G_VECREDUCE_FADD [[FADD2]](<2 x s64>)
60 ; CHECK: $x0 = COPY [[VECREDUCE_FADD]](s64)
H A Dregbankselect-reductions.mir15 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>)
16 ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32)
H A Dirtranslator-reductions.ll28 ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:_(s32) = reassoc G_VECREDUCE_FADD [[BITCAST]](<4 x s32>)
29 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = reassoc G_FADD [[COPY]], [[VECREDUCE_FADD]]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1272 VECREDUCE_FADD, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp439 case ISD::VECREDUCE_FADD: in LegalizeOp()
895 case ISD::VECREDUCE_FADD: in Expand()
H A DSelectionDAGDumper.cpp474 case ISD::VECREDUCE_FADD: return "vecreduce_fadd"; in getOperationName()
H A DLegalizeFloatTypes.cpp141 case ISD::VECREDUCE_FADD: in SoftenFloatResult()
2302 case ISD::VECREDUCE_FADD: in PromoteFloatResult()
2665 case ISD::VECREDUCE_FADD: in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp683 case ISD::VECREDUCE_FADD: in ScalarizeVectorOperand()
2757 case ISD::VECREDUCE_FADD: in SplitVectorOperand()
5473 case ISD::VECREDUCE_FADD: in WidenVectorOperand()
H A DLegalizeDAG.cpp1185 case ISD::VECREDUCE_FADD: in LegalizeOp()
3825 case ISD::VECREDUCE_FADD: in ExpandNode()
H A DSelectionDAG.cpp371 case ISD::VECREDUCE_FADD: in getVecReduceBaseOpcode()
H A DSelectionDAGBuilder.cpp9556 DAG.getNode(ISD::VECREDUCE_FADD, dl, VT, Op2, SDFlags), in visitVectorReduce()
H A DDAGCombiner.cpp1799 case ISD::VECREDUCE_FADD: in visit()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp862 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1061 setOperationAction(ISD::VECREDUCE_FADD, VT, Legal); in AArch64TargetLowering()
1317 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in AArch64TargetLowering()
1432 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in AArch64TargetLowering()
1698 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in addTypeForFixedLengthSVE()
5548 case ISD::VECREDUCE_FADD: in LowerOperation()
12173 Op.getOpcode() == ISD::VECREDUCE_FADD || in LowerVECREDUCE()
12200 case ISD::VECREDUCE_FADD: in LowerVECREDUCE()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp467 ISD::VECREDUCE_FADD, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_FMIN, in RISCVTargetLowering()
681 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in RISCVTargetLowering()
3435 case ISD::VECREDUCE_FADD: in LowerOperation()
5283 case ISD::VECREDUCE_FADD: { in getRVVFPReductionOpAndOperands()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td464 def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp356 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); in addMVEVectorTypes()
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom); in addMVEVectorTypes()
383 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom); in addMVEVectorTypes()
10140 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break; in LowerVecReduce()
10430 case ISD::VECREDUCE_FADD: in LowerOperation()