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Searched refs:VECREDUCE_AND (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dirtranslator-reductions.ll144 ; CHECK: [[VECREDUCE_AND:%[0-9]+]]:_(s32) = G_VECREDUCE_AND [[COPY]](<4 x s32>)
145 ; CHECK: $w0 = COPY [[VECREDUCE_AND]](s32)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1282 VECREDUCE_AND, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp432 case ISD::VECREDUCE_AND: in LegalizeOp()
888 case ISD::VECREDUCE_AND: in Expand()
H A DSelectionDAGDumper.cpp480 case ISD::VECREDUCE_AND: return "vecreduce_and"; in getOperationName()
H A DLegalizeIntegerTypes.cpp236 case ISD::VECREDUCE_AND: in PromoteIntegerResult()
1707 case ISD::VECREDUCE_AND: in PromoteIntegerOperand()
2230 case ISD::VECREDUCE_AND: in getExtendForIntVecReduction()
2291 else if (Opcode == ISD::VECREDUCE_AND && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2292 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_AND, InVT) && in PromoteIntOp_VECREDUCE()
2540 case ISD::VECREDUCE_AND: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp687 case ISD::VECREDUCE_AND: in ScalarizeVectorOperand()
2761 case ISD::VECREDUCE_AND: in SplitVectorOperand()
5477 case ISD::VECREDUCE_AND: in WidenVectorOperand()
H A DLegalizeDAG.cpp1189 case ISD::VECREDUCE_AND: in LegalizeOp()
3829 case ISD::VECREDUCE_AND: in ExpandNode()
H A DDAGCombiner.cpp1803 case ISD::VECREDUCE_AND: in visit()
23341 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
23342 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND in visitVECREDUCE()
23358 (Opcode == ISD::VECREDUCE_AND && in visitVECREDUCE()
H A DSelectionDAG.cpp387 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
5400 return getNode(ISD::VECREDUCE_AND, DL, VT, Operand); in getNode()
H A DSelectionDAGBuilder.cpp9576 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); in visitVectorReduce()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp462 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
507 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
781 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
3429 case ISD::VECREDUCE_AND: in LowerOperation()
5128 case ISD::VECREDUCE_AND: in getRVVReductionOp()
5143 assert((Op.getOpcode() == ISD::VECREDUCE_AND || in lowerVectorMaskVecReduction()
5177 case ISD::VECREDUCE_AND: in lowerVectorMaskVecReduction()
7379 case ISD::VECREDUCE_AND: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp863 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1181 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1227 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1420 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1697 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addTypeForFixedLengthSVE()
5541 case ISD::VECREDUCE_AND: in LowerOperation()
12170 bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND || in LowerVECREDUCE()
12186 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
21440 case ISD::VECREDUCE_AND: { in LowerPredReductionToSVE()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp339 ISD::VECREDUCE_ADD, ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, in initVPUActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp299 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addMVEVectorTypes()
10143 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in LowerVecReduce()
10426 case ISD::VECREDUCE_AND: in LowerOperation()