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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Damdgcn-ieee.ll5 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
7 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
20 ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
22 ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
37 ; GCN-NOT: [[VAL1]]
38 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
82 ; GCN-NOT: [[VAL1]]
97 ; GCN-NOT: [[VAL1]]
127 ; GCN-NOT: [[VAL1]]
142 ; GCN-NOT: [[VAL1]]
[all …]
H A Dannotate-kernel-features.ll52 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
60 ; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
75 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
83 ; ATTRIBUTOR_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
117 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()
141 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.z()
165 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
243 ; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.x()
259 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tgid.y()
283 ; AKF_CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.r600.read.tidig.y()
[all …]
H A Dpack.v2i16.ll8 ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
9 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
25 ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
26 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1c8, [[VAL1]]
56 ; GFX9: global_load_dword [[VAL1:v[0-9]+]]
59 ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]]
79 ; GFX9: global_load_dword [[VAL1:v[0-9]+]]
103 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]]
107 ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[K]]
124 ; GFX9: global_load_dword [[VAL1:v[0-9]+]]
[all …]
H A Dds_write2st64.ll31 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
34 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4 glc{{$…
38 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
60 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
63 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4
67 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
88 ; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9…
91 ; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} of…
95 ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
H A Dpack.v2f16.ll8 ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
9 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
27 ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
28 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1234, [[VAL1]]
60 ; GFX9: global_load_dword [[VAL1:v[0-9]+]]
63 ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[ELT0]]
85 ; GFX9: global_load_dword [[VAL1:v[0-9]+]]
111 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]]
114 ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[K]]
131 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]]
[all …]
H A Dannotate-kernel-features-hsa.ll57 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
65 ; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
80 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
88 ; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
122 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
146 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z()
170 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
248 ; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x()
264 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y()
288 ; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ObjCARC/
H A Dintrinsic-use.ll24 ; CHECK-NEXT: [[VAL1:%.*]] = load i8*, i8** %temp0
25 ; CHECK-NEXT: @llvm.objc.retain(i8* [[VAL1]])
28 ; CHECK-NEXT: store i8* [[VAL1]], i8** %temp1
32 ; CHECK-NEXT: call void (...) @llvm.objc.clang.arc.use(i8* [[VAL1]])
33 ; CHECK-NEXT: @llvm.objc.release(i8* [[VAL1]])
72 ; CHECK-NEXT: [[VAL1:%.*]] = load i8*, i8** %temp0
73 ; CHECK-NEXT: @llvm.objc.retain(i8* [[VAL1]])
76 ; CHECK-NEXT: store i8* [[VAL1]], i8** %temp1
80 ; CHECK-NEXT: call void (...) @llvm.objc.clang.arc.use(i8* [[VAL1]])
81 ; CHECK-NEXT: @llvm.objc.release(i8* [[VAL1]])
/llvm-project-15.0.7/lld/test/ELF/linkerscript/
H A Dearly-assign-symbol.s9 # RUN: llvm-nm -p %t | FileCheck --check-prefix=VAL1 %s
11 # VAL1: 0000000000000000 T foo
12 # VAL1: 0000000000000001 T aaa
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dprint-pragma-microsoft.c11 #define VAL1 "VAL1\"" macro
14 #pragma detect_mismatch(KEY1 KEY2, VAL1 VAL2)
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-bpf-preserve-field-info-4.c8 VAL1 = 2, enumerator
14 return _(*(enum AA *)VAL1, 0) + _(*(__BB *)VAL10, 1); in unit1()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dlarge-stack.ll36 ; CHECK-NEXT: ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
39 ; CHECK-NEXT: madd x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]]
41 ; CHECK-NEXT: str x[[TMP1]], [x[[VAL1]]]
/llvm-project-15.0.7/mlir/test/Dialect/SparseTensor/
H A Dsparse_storage.mlir36 // CHECK: %[[VAL1:.*]] = memref.load %{{.*}}[%[[INDC]]] : memref<32xf64>
37 // CHECK: %[[MUL:.*]] = arith.mulf %[[VAL0]], %[[VAL1]] : f64
65 // CHECK: %[[VAL1:.*]] = memref.load %{{.*}}[%[[INDC]]] : memref<32xf64>
66 // CHECK: %[[MUL:.*]] = arith.mulf %[[VAL0]], %[[VAL1]] : f64
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dwrong-hoisting-iv.ll13 ; CHECK-NEXT: [[VAL1:%.*]] = add i32 undef, 12
15 ; CHECK-NEXT: [[VAL3:%.*]] = mul i32 [[VAL1]], [[VAL2]]
48 ; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[VAL1]], [[VAL2]]
60 ; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[VAL1]], [[VAL2]]
72 ; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[VAL1]], [[VAL2]]
84 ; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[VAL1]], [[VAL2]]
96 ; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[VAL1]], [[VAL2]]
194 ; CHECK-NEXT: [[VAL1:%.*]] = load i32, i32* [[VAL]], align 4
210 ; CHECK-NEXT: [[VAL14:%.*]] = add i32 [[VAL8]], [[VAL1]]
211 ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[VAL1]], [[VAL8]]
/llvm-project-15.0.7/llvm/test/Transforms/Scalarizer/
H A Dvariable-insertelement.ll65 ; OFF-NEXT: [[VAL1:%.*]] = insertelement <4 x i32> [[VAL0]], i32 1, i32 [[INDEX:%.*]]
66 ; OFF-NEXT: [[VAL1_I0:%.*]] = extractelement <4 x i32> [[VAL1]], i32 0
68 ; OFF-NEXT: [[VAL1_I1:%.*]] = extractelement <4 x i32> [[VAL1]], i32 1
70 ; OFF-NEXT: [[VAL1_I2:%.*]] = extractelement <4 x i32> [[VAL1]], i32 2
72 ; OFF-NEXT: [[VAL1_I3:%.*]] = extractelement <4 x i32> [[VAL1]], i32 3
H A Dbasic.ll463 ; CHECK-NEXT: [[VAL1:%.*]] = load <32 x i1>, <32 x i1>* [[SRC1]], align 4
464 ; CHECK-NEXT: [[VAL1_I0:%.*]] = extractelement <32 x i1> [[VAL1]], i32 0
466 ; CHECK-NEXT: [[VAL1_I1:%.*]] = extractelement <32 x i1> [[VAL1]], i32 1
468 ; CHECK-NEXT: [[VAL1_I2:%.*]] = extractelement <32 x i1> [[VAL1]], i32 2
470 ; CHECK-NEXT: [[VAL1_I3:%.*]] = extractelement <32 x i1> [[VAL1]], i32 3
472 ; CHECK-NEXT: [[VAL1_I4:%.*]] = extractelement <32 x i1> [[VAL1]], i32 4
474 ; CHECK-NEXT: [[VAL1_I5:%.*]] = extractelement <32 x i1> [[VAL1]], i32 5
476 ; CHECK-NEXT: [[VAL1_I6:%.*]] = extractelement <32 x i1> [[VAL1]], i32 6
478 ; CHECK-NEXT: [[VAL1_I7:%.*]] = extractelement <32 x i1> [[VAL1]], i32 7
480 ; CHECK-NEXT: [[VAL1_I8:%.*]] = extractelement <32 x i1> [[VAL1]], i32 8
[all …]
H A Dbasic-inseltpoison.ll463 ; CHECK-NEXT: [[VAL1:%.*]] = load <32 x i1>, <32 x i1>* [[SRC1]], align 4
464 ; CHECK-NEXT: [[VAL1_I0:%.*]] = extractelement <32 x i1> [[VAL1]], i32 0
466 ; CHECK-NEXT: [[VAL1_I1:%.*]] = extractelement <32 x i1> [[VAL1]], i32 1
468 ; CHECK-NEXT: [[VAL1_I2:%.*]] = extractelement <32 x i1> [[VAL1]], i32 2
470 ; CHECK-NEXT: [[VAL1_I3:%.*]] = extractelement <32 x i1> [[VAL1]], i32 3
472 ; CHECK-NEXT: [[VAL1_I4:%.*]] = extractelement <32 x i1> [[VAL1]], i32 4
474 ; CHECK-NEXT: [[VAL1_I5:%.*]] = extractelement <32 x i1> [[VAL1]], i32 5
476 ; CHECK-NEXT: [[VAL1_I6:%.*]] = extractelement <32 x i1> [[VAL1]], i32 6
478 ; CHECK-NEXT: [[VAL1_I7:%.*]] = extractelement <32 x i1> [[VAL1]], i32 7
480 ; CHECK-NEXT: [[VAL1_I8:%.*]] = extractelement <32 x i1> [[VAL1]], i32 8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/CORE/
H A Dintrinsic-typeinfo-enum-value.ll6 ; enum AA { VAL1 = -100, VAL2 = 0xffff8000 };
9 ; return __builtin_preserve_enum_value(*(enum AA *)VAL1, 0) +
18 @0 = private unnamed_addr constant [10 x i8] c"VAL1:-100\00", align 1
60 ; CHECK: .ascii "VAL1" # string offset=19
99 !6 = !DIEnumerator(name: "VAL1", value: -100)
H A Dintrinsic-typeinfo-enum-value-opaque-pointer.ll6 ; enum AA { VAL1 = -100, VAL2 = 0xffff8000 };
9 ; return __builtin_preserve_enum_value(*(enum AA *)VAL1, 0) +
18 @0 = private unnamed_addr constant [10 x i8] c"VAL1:-100\00", align 1
80 !6 = !DIEnumerator(name: "VAL1", value: -100)
/llvm-project-15.0.7/clang/test/Sema/
H A Dbuiltins-bpf.c19 VAL1 = 10, enumerator
90 return __builtin_preserve_enum_value(*(enum AA *)VAL1, 1) + in valid15()
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dunreachable-predecessor.ll10 ; CHECK: %[[VAL1:.*]] = load i32, i32* %[[GEP]]
32 ; CHECK: store i32 %[[VAL1]], i32* %phi2
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Deliminate-congruent-ivs.ll50 ; CHECK-NEXT: [[VAL1:%.*]] = phi i64 [ [[VAL1_INC:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
51 ; CHECK-NEXT: [[VAL1_INC]] = add nuw nsw i64 [[VAL1]], 1
53 ; CHECK-NEXT: call void @foo(i64 [[VAL1]])
54 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i64 [[VAL1]], 1000
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A Dnon-byte-size.ll13 ; CHECK-NEXT: [[VAL1:%.*]] = load i32, i32* [[IN1]], align 8
17 ; CHECK-NEXT: store i32 [[VAL1]], i32* [[OUT1]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dmerge-cond-stores-cost.ll17 ; CHECK-NEXT: [[VAL1:%.*]] = sdiv i32 [[C]], [[D]]
18 ; CHECK-NEXT: store i32 [[VAL1]], i32* [[P]], align 4
/llvm-project-15.0.7/llvm/test/TableGen/
H A DDag.td12 def VAL1 : C1<13>;
14 // CHECK: def VAL1 {
/llvm-project-15.0.7/llvm/test/Transforms/RewriteStatepointsForGC/
H A Dbasic.ll53 ; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.experimental.gc.result.i32(token [[STATEPOINT_TOKEN]…
56 ; CHECK-NEXT: store i32 [[VAL1]], i32 addrspace(1)* [[ARG_RELOCATED_CASTED]], align 4
73 ; CHECK-NEXT: [[VAL1:%.*]] = call i32 @llvm.experimental.gc.result.i32(token [[STATEPOINT_TOKEN]…
76 ; CHECK-NEXT: store i32 [[VAL1]], i32 addrspace(1)* [[ARG_RELOCATED2_CASTED]], align 4

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