1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals 2; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefixes=HSA,AKF_HSA %s 3; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-attributor < %s | FileCheck -check-prefixes=HSA,ATTRIBUTOR_HSA %s 4 5target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" 6 7declare i32 @llvm.amdgcn.workgroup.id.x() #0 8declare i32 @llvm.amdgcn.workgroup.id.y() #0 9declare i32 @llvm.amdgcn.workgroup.id.z() #0 10 11declare i32 @llvm.amdgcn.workitem.id.x() #0 12declare i32 @llvm.amdgcn.workitem.id.y() #0 13declare i32 @llvm.amdgcn.workitem.id.z() #0 14 15declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 16declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 17declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 18 19declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #2 20declare i1 @llvm.amdgcn.is.private(i8* nocapture) #2 21 22define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { 23; HSA-LABEL: define {{[^@]+}}@use_tgid_x 24; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1:[0-9]+]] { 25; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 26; HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 27; HSA-NEXT: ret void 28; 29 %val = call i32 @llvm.amdgcn.workgroup.id.x() 30 store i32 %val, i32 addrspace(1)* %ptr 31 ret void 32} 33 34define amdgpu_kernel void @use_tgid_y(i32 addrspace(1)* %ptr) #1 { 35; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_y 36; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 37; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 38; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 39; AKF_HSA-NEXT: ret void 40; 41; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_y 42; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR2:[0-9]+]] { 43; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 44; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 45; ATTRIBUTOR_HSA-NEXT: ret void 46; 47 %val = call i32 @llvm.amdgcn.workgroup.id.y() 48 store i32 %val, i32 addrspace(1)* %ptr 49 ret void 50} 51 52define amdgpu_kernel void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #1 { 53; AKF_HSA-LABEL: define {{[^@]+}}@multi_use_tgid_y 54; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 55; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 56; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 57; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 58; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 59; AKF_HSA-NEXT: ret void 60; 61; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@multi_use_tgid_y 62; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR2]] { 63; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 64; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 65; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 66; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 67; ATTRIBUTOR_HSA-NEXT: ret void 68; 69 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 70 store volatile i32 %val0, i32 addrspace(1)* %ptr 71 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 72 store volatile i32 %val1, i32 addrspace(1)* %ptr 73 ret void 74} 75 76define amdgpu_kernel void @use_tgid_x_y(i32 addrspace(1)* %ptr) #1 { 77; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y 78; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 79; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 80; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 81; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 82; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 83; AKF_HSA-NEXT: ret void 84; 85; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y 86; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR2]] { 87; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 88; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 89; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 90; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 91; ATTRIBUTOR_HSA-NEXT: ret void 92; 93 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 94 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 95 store volatile i32 %val0, i32 addrspace(1)* %ptr 96 store volatile i32 %val1, i32 addrspace(1)* %ptr 97 ret void 98} 99 100define amdgpu_kernel void @use_tgid_z(i32 addrspace(1)* %ptr) #1 { 101; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_z 102; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 103; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 104; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 105; AKF_HSA-NEXT: ret void 106; 107; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_z 108; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR3:[0-9]+]] { 109; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 110; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 111; ATTRIBUTOR_HSA-NEXT: ret void 112; 113 %val = call i32 @llvm.amdgcn.workgroup.id.z() 114 store i32 %val, i32 addrspace(1)* %ptr 115 ret void 116} 117 118define amdgpu_kernel void @use_tgid_x_z(i32 addrspace(1)* %ptr) #1 { 119; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_z 120; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 121; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 122; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 123; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 124; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 125; AKF_HSA-NEXT: ret void 126; 127; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_z 128; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR3]] { 129; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 130; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 131; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 132; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 133; ATTRIBUTOR_HSA-NEXT: ret void 134; 135 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 136 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 137 store volatile i32 %val0, i32 addrspace(1)* %ptr 138 store volatile i32 %val1, i32 addrspace(1)* %ptr 139 ret void 140} 141 142define amdgpu_kernel void @use_tgid_y_z(i32 addrspace(1)* %ptr) #1 { 143; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_y_z 144; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 145; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 146; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 147; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 148; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 149; AKF_HSA-NEXT: ret void 150; 151; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_y_z 152; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR4:[0-9]+]] { 153; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 154; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 155; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 156; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 157; ATTRIBUTOR_HSA-NEXT: ret void 158; 159 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 160 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 161 store volatile i32 %val0, i32 addrspace(1)* %ptr 162 store volatile i32 %val1, i32 addrspace(1)* %ptr 163 ret void 164} 165 166define amdgpu_kernel void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #1 { 167; AKF_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y_z 168; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 169; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 170; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 171; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 172; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 173; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 174; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 175; AKF_HSA-NEXT: ret void 176; 177; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tgid_x_y_z 178; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR4]] { 179; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 180; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 181; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 182; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 183; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 184; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 185; ATTRIBUTOR_HSA-NEXT: ret void 186; 187 %val0 = call i32 @llvm.amdgcn.workgroup.id.x() 188 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 189 %val2 = call i32 @llvm.amdgcn.workgroup.id.z() 190 store volatile i32 %val0, i32 addrspace(1)* %ptr 191 store volatile i32 %val1, i32 addrspace(1)* %ptr 192 store volatile i32 %val2, i32 addrspace(1)* %ptr 193 ret void 194} 195 196define amdgpu_kernel void @use_tidig_x(i32 addrspace(1)* %ptr) #1 { 197; HSA-LABEL: define {{[^@]+}}@use_tidig_x 198; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 199; HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 200; HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 201; HSA-NEXT: ret void 202; 203 %val = call i32 @llvm.amdgcn.workitem.id.x() 204 store i32 %val, i32 addrspace(1)* %ptr 205 ret void 206} 207 208define amdgpu_kernel void @use_tidig_y(i32 addrspace(1)* %ptr) #1 { 209; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_y 210; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 211; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 212; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 213; AKF_HSA-NEXT: ret void 214; 215; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_y 216; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR5:[0-9]+]] { 217; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 218; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 219; ATTRIBUTOR_HSA-NEXT: ret void 220; 221 %val = call i32 @llvm.amdgcn.workitem.id.y() 222 store i32 %val, i32 addrspace(1)* %ptr 223 ret void 224} 225 226define amdgpu_kernel void @use_tidig_z(i32 addrspace(1)* %ptr) #1 { 227; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_z 228; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 229; AKF_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 230; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 231; AKF_HSA-NEXT: ret void 232; 233; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_z 234; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR6:[0-9]+]] { 235; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 236; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 237; ATTRIBUTOR_HSA-NEXT: ret void 238; 239 %val = call i32 @llvm.amdgcn.workitem.id.z() 240 store i32 %val, i32 addrspace(1)* %ptr 241 ret void 242} 243 244define amdgpu_kernel void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 { 245; HSA-LABEL: define {{[^@]+}}@use_tidig_x_tgid_x 246; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 247; HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 248; HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 249; HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 250; HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 251; HSA-NEXT: ret void 252; 253 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 254 %val1 = call i32 @llvm.amdgcn.workgroup.id.x() 255 store volatile i32 %val0, i32 addrspace(1)* %ptr 256 store volatile i32 %val1, i32 addrspace(1)* %ptr 257 ret void 258} 259 260define amdgpu_kernel void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #1 { 261; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 262; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 263; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 264; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 265; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 266; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 267; AKF_HSA-NEXT: ret void 268; 269; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_y_tgid_y 270; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR7:[0-9]+]] { 271; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 272; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 273; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 274; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 275; ATTRIBUTOR_HSA-NEXT: ret void 276; 277 %val0 = call i32 @llvm.amdgcn.workitem.id.y() 278 %val1 = call i32 @llvm.amdgcn.workgroup.id.y() 279 store volatile i32 %val0, i32 addrspace(1)* %ptr 280 store volatile i32 %val1, i32 addrspace(1)* %ptr 281 ret void 282} 283 284define amdgpu_kernel void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #1 { 285; AKF_HSA-LABEL: define {{[^@]+}}@use_tidig_x_y_z 286; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 287; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 288; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 289; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 290; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 291; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 292; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 293; AKF_HSA-NEXT: ret void 294; 295; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_tidig_x_y_z 296; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR8:[0-9]+]] { 297; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 298; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 299; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 300; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 301; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 302; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 303; ATTRIBUTOR_HSA-NEXT: ret void 304; 305 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 306 %val1 = call i32 @llvm.amdgcn.workitem.id.y() 307 %val2 = call i32 @llvm.amdgcn.workitem.id.z() 308 store volatile i32 %val0, i32 addrspace(1)* %ptr 309 store volatile i32 %val1, i32 addrspace(1)* %ptr 310 store volatile i32 %val2, i32 addrspace(1)* %ptr 311 ret void 312} 313 314define amdgpu_kernel void @use_all_workitems(i32 addrspace(1)* %ptr) #1 { 315; AKF_HSA-LABEL: define {{[^@]+}}@use_all_workitems 316; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 317; AKF_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 318; AKF_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 319; AKF_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 320; AKF_HSA-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 321; AKF_HSA-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 322; AKF_HSA-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 323; AKF_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 324; AKF_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 325; AKF_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 326; AKF_HSA-NEXT: store volatile i32 [[VAL3]], i32 addrspace(1)* [[PTR]], align 4 327; AKF_HSA-NEXT: store volatile i32 [[VAL4]], i32 addrspace(1)* [[PTR]], align 4 328; AKF_HSA-NEXT: store volatile i32 [[VAL5]], i32 addrspace(1)* [[PTR]], align 4 329; AKF_HSA-NEXT: ret void 330; 331; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_all_workitems 332; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR9:[0-9]+]] { 333; ATTRIBUTOR_HSA-NEXT: [[VAL0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 334; ATTRIBUTOR_HSA-NEXT: [[VAL1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() 335; ATTRIBUTOR_HSA-NEXT: [[VAL2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() 336; ATTRIBUTOR_HSA-NEXT: [[VAL3:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() 337; ATTRIBUTOR_HSA-NEXT: [[VAL4:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() 338; ATTRIBUTOR_HSA-NEXT: [[VAL5:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() 339; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL0]], i32 addrspace(1)* [[PTR]], align 4 340; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL1]], i32 addrspace(1)* [[PTR]], align 4 341; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL2]], i32 addrspace(1)* [[PTR]], align 4 342; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL3]], i32 addrspace(1)* [[PTR]], align 4 343; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL4]], i32 addrspace(1)* [[PTR]], align 4 344; ATTRIBUTOR_HSA-NEXT: store volatile i32 [[VAL5]], i32 addrspace(1)* [[PTR]], align 4 345; ATTRIBUTOR_HSA-NEXT: ret void 346; 347 %val0 = call i32 @llvm.amdgcn.workitem.id.x() 348 %val1 = call i32 @llvm.amdgcn.workitem.id.y() 349 %val2 = call i32 @llvm.amdgcn.workitem.id.z() 350 %val3 = call i32 @llvm.amdgcn.workgroup.id.x() 351 %val4 = call i32 @llvm.amdgcn.workgroup.id.y() 352 %val5 = call i32 @llvm.amdgcn.workgroup.id.z() 353 store volatile i32 %val0, i32 addrspace(1)* %ptr 354 store volatile i32 %val1, i32 addrspace(1)* %ptr 355 store volatile i32 %val2, i32 addrspace(1)* %ptr 356 store volatile i32 %val3, i32 addrspace(1)* %ptr 357 store volatile i32 %val4, i32 addrspace(1)* %ptr 358 store volatile i32 %val5, i32 addrspace(1)* %ptr 359 ret void 360} 361 362define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { 363; AKF_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr 364; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 365; AKF_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 366; AKF_HSA-NEXT: [[BC:%.*]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)* 367; AKF_HSA-NEXT: [[VAL:%.*]] = load i32, i32 addrspace(4)* [[BC]], align 4 368; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 369; AKF_HSA-NEXT: ret void 370; 371; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_dispatch_ptr 372; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR10:[0-9]+]] { 373; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 374; ATTRIBUTOR_HSA-NEXT: [[BC:%.*]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)* 375; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = load i32, i32 addrspace(4)* [[BC]], align 4 376; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 377; ATTRIBUTOR_HSA-NEXT: ret void 378; 379 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 380 %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)* 381 %val = load i32, i32 addrspace(4)* %bc 382 store i32 %val, i32 addrspace(1)* %ptr 383 ret void 384} 385 386define amdgpu_kernel void @use_queue_ptr(i32 addrspace(1)* %ptr) #1 { 387; AKF_HSA-LABEL: define {{[^@]+}}@use_queue_ptr 388; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 389; AKF_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 390; AKF_HSA-NEXT: [[BC:%.*]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)* 391; AKF_HSA-NEXT: [[VAL:%.*]] = load i32, i32 addrspace(4)* [[BC]], align 4 392; AKF_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 393; AKF_HSA-NEXT: ret void 394; 395; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_queue_ptr 396; ATTRIBUTOR_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR11:[0-9]+]] { 397; ATTRIBUTOR_HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 398; ATTRIBUTOR_HSA-NEXT: [[BC:%.*]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)* 399; ATTRIBUTOR_HSA-NEXT: [[VAL:%.*]] = load i32, i32 addrspace(4)* [[BC]], align 4 400; ATTRIBUTOR_HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 401; ATTRIBUTOR_HSA-NEXT: ret void 402; 403 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 404 %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)* 405 %val = load i32, i32 addrspace(4)* %bc 406 store i32 %val, i32 addrspace(1)* %ptr 407 ret void 408} 409 410define amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #1 { 411; HSA-LABEL: define {{[^@]+}}@use_kernarg_segment_ptr 412; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 413; HSA-NEXT: [[DISPATCH_PTR:%.*]] = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 414; HSA-NEXT: [[BC:%.*]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)* 415; HSA-NEXT: [[VAL:%.*]] = load i32, i32 addrspace(4)* [[BC]], align 4 416; HSA-NEXT: store i32 [[VAL]], i32 addrspace(1)* [[PTR]], align 4 417; HSA-NEXT: ret void 418; 419 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 420 %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)* 421 %val = load i32, i32 addrspace(4)* %bc 422 store i32 %val, i32 addrspace(1)* %ptr 423 ret void 424} 425 426define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { 427; AKF_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast 428; AKF_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR1]] { 429; AKF_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32* 430; AKF_HSA-NEXT: store volatile i32 0, i32* [[STOF]], align 4 431; AKF_HSA-NEXT: ret void 432; 433; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_group_to_flat_addrspacecast 434; ATTRIBUTOR_HSA-SAME: (i32 addrspace(3)* [[PTR:%.*]]) #[[ATTR11]] { 435; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(3)* [[PTR]] to i32* 436; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32* [[STOF]], align 4 437; ATTRIBUTOR_HSA-NEXT: ret void 438; 439 %stof = addrspacecast i32 addrspace(3)* %ptr to i32* 440 store volatile i32 0, i32* %stof 441 ret void 442} 443 444define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #1 { 445; AKF_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast 446; AKF_HSA-SAME: (i32 addrspace(5)* [[PTR:%.*]]) #[[ATTR1]] { 447; AKF_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(5)* [[PTR]] to i32* 448; AKF_HSA-NEXT: store volatile i32 0, i32* [[STOF]], align 4 449; AKF_HSA-NEXT: ret void 450; 451; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast 452; ATTRIBUTOR_HSA-SAME: (i32 addrspace(5)* [[PTR:%.*]]) #[[ATTR11]] { 453; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(5)* [[PTR]] to i32* 454; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, i32* [[STOF]], align 4 455; ATTRIBUTOR_HSA-NEXT: ret void 456; 457 %stof = addrspacecast i32 addrspace(5)* %ptr to i32* 458 store volatile i32 0, i32* %stof 459 ret void 460} 461 462define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #1 { 463; HSA-LABEL: define {{[^@]+}}@use_flat_to_group_addrspacecast 464; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] { 465; HSA-NEXT: [[FTOS:%.*]] = addrspacecast i32* [[PTR]] to i32 addrspace(3)* 466; HSA-NEXT: store volatile i32 0, i32 addrspace(3)* [[FTOS]], align 4 467; HSA-NEXT: ret void 468; 469 %ftos = addrspacecast i32* %ptr to i32 addrspace(3)* 470 store volatile i32 0, i32 addrspace(3)* %ftos 471 ret void 472} 473 474define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #1 { 475; HSA-LABEL: define {{[^@]+}}@use_flat_to_private_addrspacecast 476; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] { 477; HSA-NEXT: [[FTOS:%.*]] = addrspacecast i32* [[PTR]] to i32 addrspace(5)* 478; HSA-NEXT: store volatile i32 0, i32 addrspace(5)* [[FTOS]], align 4 479; HSA-NEXT: ret void 480; 481 %ftos = addrspacecast i32* %ptr to i32 addrspace(5)* 482 store volatile i32 0, i32 addrspace(5)* %ftos 483 ret void 484} 485 486; No-op addrspacecast should not use queue ptr 487define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { 488; HSA-LABEL: define {{[^@]+}}@use_global_to_flat_addrspacecast 489; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] { 490; HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(1)* [[PTR]] to i32* 491; HSA-NEXT: store volatile i32 0, i32* [[STOF]], align 4 492; HSA-NEXT: ret void 493; 494 %stof = addrspacecast i32 addrspace(1)* %ptr to i32* 495 store volatile i32 0, i32* %stof 496 ret void 497} 498 499define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #1 { 500; HSA-LABEL: define {{[^@]+}}@use_constant_to_flat_addrspacecast 501; HSA-SAME: (i32 addrspace(4)* [[PTR:%.*]]) #[[ATTR1]] { 502; HSA-NEXT: [[STOF:%.*]] = addrspacecast i32 addrspace(4)* [[PTR]] to i32* 503; HSA-NEXT: [[LD:%.*]] = load volatile i32, i32* [[STOF]], align 4 504; HSA-NEXT: ret void 505; 506 %stof = addrspacecast i32 addrspace(4)* %ptr to i32* 507 %ld = load volatile i32, i32* %stof 508 ret void 509} 510 511define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 { 512; HSA-LABEL: define {{[^@]+}}@use_flat_to_global_addrspacecast 513; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] { 514; HSA-NEXT: [[FTOS:%.*]] = addrspacecast i32* [[PTR]] to i32 addrspace(1)* 515; HSA-NEXT: store volatile i32 0, i32 addrspace(1)* [[FTOS]], align 4 516; HSA-NEXT: ret void 517; 518 %ftos = addrspacecast i32* %ptr to i32 addrspace(1)* 519 store volatile i32 0, i32 addrspace(1)* %ftos 520 ret void 521} 522 523define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 { 524; HSA-LABEL: define {{[^@]+}}@use_flat_to_constant_addrspacecast 525; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] { 526; HSA-NEXT: [[FTOS:%.*]] = addrspacecast i32* [[PTR]] to i32 addrspace(4)* 527; HSA-NEXT: [[LD:%.*]] = load volatile i32, i32 addrspace(4)* [[FTOS]], align 4 528; HSA-NEXT: ret void 529; 530 %ftos = addrspacecast i32* %ptr to i32 addrspace(4)* 531 %ld = load volatile i32, i32 addrspace(4)* %ftos 532 ret void 533} 534 535define amdgpu_kernel void @use_is_shared(i8* %ptr) #1 { 536; AKF_HSA-LABEL: define {{[^@]+}}@use_is_shared 537; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] { 538; AKF_HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[PTR]]) 539; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32 540; AKF_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4 541; AKF_HSA-NEXT: ret void 542; 543; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_shared 544; ATTRIBUTOR_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] { 545; ATTRIBUTOR_HSA-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[PTR]]) 546; ATTRIBUTOR_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_SHARED]] to i32 547; ATTRIBUTOR_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4 548; ATTRIBUTOR_HSA-NEXT: ret void 549; 550 %is.shared = call i1 @llvm.amdgcn.is.shared(i8* %ptr) 551 %ext = zext i1 %is.shared to i32 552 store i32 %ext, i32 addrspace(1)* undef 553 ret void 554} 555 556define amdgpu_kernel void @use_is_private(i8* %ptr) #1 { 557; AKF_HSA-LABEL: define {{[^@]+}}@use_is_private 558; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] { 559; AKF_HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[PTR]]) 560; AKF_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32 561; AKF_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4 562; AKF_HSA-NEXT: ret void 563; 564; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_is_private 565; ATTRIBUTOR_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] { 566; ATTRIBUTOR_HSA-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[PTR]]) 567; ATTRIBUTOR_HSA-NEXT: [[EXT:%.*]] = zext i1 [[IS_PRIVATE]] to i32 568; ATTRIBUTOR_HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* undef, align 4 569; ATTRIBUTOR_HSA-NEXT: ret void 570; 571 %is.private = call i1 @llvm.amdgcn.is.private(i8* %ptr) 572 %ext = zext i1 %is.private to i32 573 store i32 %ext, i32 addrspace(1)* undef 574 ret void 575} 576 577define amdgpu_kernel void @use_alloca() #1 { 578; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca 579; AKF_HSA-SAME: () #[[ATTR2:[0-9]+]] { 580; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 581; AKF_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 582; AKF_HSA-NEXT: ret void 583; 584; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca 585; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 586; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 587; ATTRIBUTOR_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 588; ATTRIBUTOR_HSA-NEXT: ret void 589; 590 %alloca = alloca i32, addrspace(5) 591 store i32 0, i32 addrspace(5)* %alloca 592 ret void 593} 594 595define amdgpu_kernel void @use_alloca_non_entry_block() #1 { 596; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca_non_entry_block 597; AKF_HSA-SAME: () #[[ATTR2]] { 598; AKF_HSA-NEXT: entry: 599; AKF_HSA-NEXT: br label [[BB:%.*]] 600; AKF_HSA: bb: 601; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 602; AKF_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 603; AKF_HSA-NEXT: ret void 604; 605; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca_non_entry_block 606; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 607; ATTRIBUTOR_HSA-NEXT: entry: 608; ATTRIBUTOR_HSA-NEXT: br label [[BB:%.*]] 609; ATTRIBUTOR_HSA: bb: 610; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 611; ATTRIBUTOR_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 612; ATTRIBUTOR_HSA-NEXT: ret void 613; 614entry: 615 br label %bb 616 617bb: 618 %alloca = alloca i32, addrspace(5) 619 store i32 0, i32 addrspace(5)* %alloca 620 ret void 621} 622 623define void @use_alloca_func() #1 { 624; AKF_HSA-LABEL: define {{[^@]+}}@use_alloca_func 625; AKF_HSA-SAME: () #[[ATTR2]] { 626; AKF_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 627; AKF_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 628; AKF_HSA-NEXT: ret void 629; 630; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_alloca_func 631; ATTRIBUTOR_HSA-SAME: () #[[ATTR1]] { 632; ATTRIBUTOR_HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) 633; ATTRIBUTOR_HSA-NEXT: store i32 0, i32 addrspace(5)* [[ALLOCA]], align 4 634; ATTRIBUTOR_HSA-NEXT: ret void 635; 636 %alloca = alloca i32, addrspace(5) 637 store i32 0, i32 addrspace(5)* %alloca 638 ret void 639} 640 641attributes #0 = { nounwind readnone speculatable } 642attributes #1 = { nounwind } 643 644;. 645; AKF_HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn } 646; AKF_HSA: attributes #[[ATTR1]] = { nounwind } 647; AKF_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-stack-objects" } 648;. 649; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nounwind readnone speculatable willreturn } 650; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 651; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 652; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 653; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 654; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 655; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } 656; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 657; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 658; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } 659; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 660; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } 661;. 662