| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 259 Register UseReg; in addLinkerOpt() member
303 Pair.UseReg = BBI->getOperand(0).getReg(); in addLinkerOpt()
321 if (BBI->readsRegister(Pair->UseReg, TRI) || in addLinkerOpt()
322 BBI->modifiesRegister(Pair->UseReg, TRI)) { in addLinkerOpt()
338 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
340 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
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| H A D | PPCVSXSwapRemoval.cpp | 724 Register UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
725 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
801 Register UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
802 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTaggingPreRA.cpp | 277 Register UseReg = WorkList.pop_back_val(); in findFirstSlotCandidate() local
278 for (auto &UseI : MRI->use_instructions(UseReg)) { in findFirstSlotCandidate()
293 << Register::virtReg2Index(UseReg) << " in " << UseI in findFirstSlotCandidate()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 243 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
246 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
252 static Register UseReg(const MachineOperand& MO) { in UseReg() function
263 Register I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
330 Register I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 486 Register UseReg, uint8_t OpTy, in getRegSeqInit() argument
488 MachineInstr *Def = MRI.getVRegDef(UseReg); in getRegSeqInit()
543 Register UseReg = OpToFold.getReg(); in tryToFoldACImm() local
544 if (!UseReg.isVirtual()) in tryToFoldACImm()
553 MachineInstr *Def = MRI.getVRegDef(UseReg); in tryToFoldACImm()
565 if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI)) in tryToFoldACImm()
733 Register UseReg = OpToFold.getReg(); in foldOperand() local
734 UseMI->getOperand(1).setReg(UseReg); in foldOperand()
746 getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII, in foldOperand()
922 Register UseReg = UseOp.getReg(); in foldOperand() local
[all …]
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| H A D | GCNHazardRecognizer.cpp | 937 Register UseReg; in checkVALUHazards() local
938 auto IsVALUDefSGPRFn = [&UseReg, TRI](const MachineInstr &MI) { in checkVALUHazards()
941 return MI.modifiesRegister(UseReg, TRI); in checkVALUHazards()
948 UseReg = Use.getReg(); in checkVALUHazards()
949 if (TRI->isSGPRReg(MRI, UseReg)) { in checkVALUHazards()
959 UseReg = AMDGPU::VCC; in checkVALUHazards()
970 UseReg = Src->getReg(); in checkVALUHazards()
978 UseReg = AMDGPU::EXEC; in checkVALUHazards()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 726 unsigned UseReg = MO.getReg(); in getMachineOpValue() local
750 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { in getMachineOpValue()
769 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); in getMachineOpValue()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 206 unsigned ARMSelectCallOp(bool UseReg);
2174 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2175 if (UseReg) in ARMSelectCallOp()
2388 bool UseReg = false; in SelectCall() local
2390 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2393 if (UseReg) { in SelectCall()
2403 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2410 if (UseReg) { in SelectCall()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 910 Register UseReg = SubsequentUse->getReg(); in runOnMachineFunction() local
912 if (DefReg != UseReg || !MRI.hasOneUse(DefReg)) in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 403 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
406 let Uses = [UseReg];
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| H A D | MipsInstrInfo.td | 1727 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1730 let Uses = [UseReg];
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