Home
last modified time | relevance | path

Searched refs:UseRC (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp102 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local
107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
137 if (!UseRC) in EmitCopyFromReg()
138 UseRC = RC; in EmitCopyFromReg()
141 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg()
145 UseRC = ComRC; in EmitCopyFromReg()
161 } else if (UseRC) { in EmitCopyFromReg()
162 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg()
164 DstRC = UseRC; in EmitCopyFromReg()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp464 const TargetRegisterClass *UseRC = in PPCEmitLoad() local
472 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
492 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
511 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad()
512 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad()
522 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
2432 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local
2436 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); in fastEmitInst_ri()
2445 const TargetRegisterClass *UseRC = in fastEmitInst_r() local
2449 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); in fastEmitInst_r()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp819 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg()); in processPHINode() local
821 UseRC != &AMDGPU::VReg_1RegClass) in processPHINode()
H A DSIFoldOperands.cpp923 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg); in foldOperand() local
925 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64) in foldOperand()