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Searched refs:UNINDEXED (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h2312 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2315 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2449 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2452 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2622 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2625 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
3028 Ld->getAddressingMode() == ISD::UNINDEXED;
3058 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
3066 St->getAddressingMode() == ISD::UNINDEXED;
3072 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
H A DISDOpcodes.h1373 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h180 return ISD::UNINDEXED; in getISDIndexedMode()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7795 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
7907 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
7916 ISD::UNINDEXED, false, VT, MMO); in getStore()
7974 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
8051 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP()
8145 bool Indexed = AM != ISD::UNINDEXED; in getStoreVP()
8206 EVL, VT, MMO, ISD::UNINDEXED, in getTruncStoreVP()
8302 bool Indexed = AM != ISD::UNINDEXED; in getStridedLoadVP()
8399 bool Indexed = AM != ISD::UNINDEXED; in getStridedStoreVP()
8621 bool Indexed = AM != ISD::UNINDEXED; in getMaskedLoad()
[all …]
H A DLegalizeVectorTypes.cpp370 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
1824 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1831 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI, in SplitVecRes_LOAD()
H A DSelectionDAGBuilder.cpp4343 ISD::UNINDEXED, false /* Truncating */, IsCompressing); in visitMaskedStore()
4517 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); in visitMaskedLoad()
7470 OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, in visitVPStoreScatter()
7548 OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, in visitVPStridedStore()
H A DTargetLowering.cpp8367 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
8519 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
H A DDAGCombiner.cpp16240 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
16534 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
16576 assert(AM != ISD::UNINDEXED); in SplitIndexingFromLoad()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2187 Thru.first, SingleTy, MOp0, ISD::UNINDEXED, in SplitHvxMemOp()
2191 Thru.second, SingleTy, MOp1, ISD::UNINDEXED, in SplitHvxMemOp()
2202 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
2205 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
2240 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in WidenHvxLoad()
2276 MemOp, ISD::UNINDEXED, false, false); in WidenHvxStore()
H A DHexagonISelDAGToDAG.cpp451 if (AM != ISD::UNINDEXED) { in SelectLoad()
560 if (AM != ISD::UNINDEXED) { in SelectStore()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1585 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1691 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()
1750 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
1766 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
H A DARMISelLowering.cpp17538 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingToWideningLoad()
18462 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingMVEEXTToWideningLoad()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td826 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
827 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1494 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
H A DSIISelLowering.cpp8568 ISD::UNINDEXED, ISD::NON_EXTLOAD, MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst1289 ST->getAddressingMode() == ISD::UNINDEXED;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp829 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
H A DX86ISelLowering.cpp28122 MemVT, MemIntr->getMemOperand(), ISD::UNINDEXED, in LowerINTRINSIC_W_CHAIN()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16932 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in performLDNT1Combine()
17004 ISD::UNINDEXED, false, false); in performSTNT1Combine()