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Searched refs:Tmp3 (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp73 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
79 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
85 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
101 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
126 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
136 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp365 SDValue Tmp3 = Idx; in PerformInsertVectorEltInMemory() local
1697 SDValue Tmp3 = Node->getOperand(2); in ExpandDYNAMIC_STACKALLOC() local
2695 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
3533 Tmp3 = Node->getOperand(2); in ExpandNode()
3536 Tmp2, Tmp3, in ExpandNode()
3605 Tmp3 = Tmp2; in ExpandNode()
3641 if (Tmp3.getNode()) { in ExpandNode()
3746 std::swap(Tmp3, Tmp4); in ExpandNode()
4467 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in PromoteNode() local
4831 Results.push_back(Tmp3); in PromoteNode()
[all …]
H A DTargetLowering.cpp7300 SDValue Tmp2, Tmp3; in expandShiftParts() local
8098 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, in expandBSWAP()
8101 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in expandBSWAP()
8121 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, in expandBSWAP()
8142 SDValue Tmp, Tmp2, Tmp3; in expandBITREVERSE() local
8160 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT)); in expandBITREVERSE()
8161 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in expandBITREVERSE()
8167 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT)); in expandBITREVERSE()
8168 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in expandBITREVERSE()
8174 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT)); in expandBITREVERSE()
[all …]
H A DLegalizeFloatTypes.cpp1846 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
1853 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1862 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3877 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3913 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3946 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4218 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
4604 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in tryVPTESTM() local
4607 Tmp3, Tmp4); in tryVPTESTM()
5104 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5157 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5239 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5373 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp133 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
134 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
281 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
349 R_1->addIncoming(Tmp3, Preheader); in generateUnsignedDivisionCode()
/llvm-project-15.0.7/llvm/unittests/IR/
H A DPassManagerTest.cpp380 auto Tmp3 = PA1; in TEST() local
381 Intersected.intersect(std::move(Tmp3)); in TEST()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGExprComplex.cpp857 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
868 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
871 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2456 SDValue Tmp3 = ST->getValue(); in LowerSTOREi1() local
2457 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"); in LowerSTOREi1()
2458 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
2460 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2108 Register Tmp3 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2116 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2121 .addReg(Tmp3, getKillRegState(true)) in prepareSymbol()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2302 SDValue Tmp3 = in lowerVAARG() local
2307 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, in lowerVAARG()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8840 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
8841 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
8869 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
8870 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
8897 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
8898 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp3366 SDValue Tmp3 = Op.getOperand(2); in lowerDYNAMIC_STACKALLOCImpl() local
3378 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue(); in lowerDYNAMIC_STACKALLOCImpl()
10373 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine() local
10375 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3); in performIntMed3ImmCombine()