Home
last modified time | relevance | path

Searched refs:TestReg (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A Dambiguous-composition.td24 class TestReg<string n, list<Register> s> : RegisterWithSubRegs<n, s> {
43 class FPR32<string n> : TestReg<n, []> {
46 class FPR64<string n, FPR32 high> : TestReg<n, [high]> {
50 class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {
54 class VPR128<string n, FPR64 high> : TestReg<n, [high]> {
75 class GPR32<string n> : TestReg<n, []> {
78 class GPR64<string n, GPR32 low> : TestReg<n, [low]> {
82 class GPR128<string n, GPR64 low> : TestReg<n, [low]> {
H A DConstraintChecking.inc9 class TestReg<string name, bits<1> enc> : Register<name, []> {
14 def R0 : TestReg<"R0", 0>;
15 def R1 : TestReg<"R1", 1>;
H A DHwModeSelect.td18 def TestReg : Register<"testreg">;
19 def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>;
H A DDAGDefaultOps.td18 class TestReg<int index> : Register<"R"#index, []> {
23 def "R"#i : TestReg<i>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1392 Register TestReg; in getTestBitReg() local
1429 if (!C || !TestReg.isValid()) in getTestBitReg()
1442 NextReg = TestReg; in getTestBitReg()
1448 NextReg = TestReg; in getTestBitReg()
1455 NextReg = TestReg; in getTestBitReg()
1463 NextReg = TestReg; in getTestBitReg()
1478 NextReg = TestReg; in getTestBitReg()
1494 assert(TestReg.isValid()); in emitTestBit()
1500 TestReg = getTestBitReg(TestReg, Bit, IsNegative, MRI); in emitTestBit()
1501 LLT Ty = MRI.getType(TestReg); in emitTestBit()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp939 TestReg = InProlog ? X86::RDX in emitStackProbeInlineWindowsCoreCLR64() local
999 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg) in emitStackProbeInlineWindowsCoreCLR64()
1003 .addReg(TestReg) in emitStackProbeInlineWindowsCoreCLR64()