| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 93 const TargetRegisterClass *
133 const TargetRegisterClass *
176 const TargetRegisterClass *
239 const TargetRegisterClass *
243 const TargetRegisterClass *
247 const TargetRegisterClass *
253 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
260 const TargetRegisterClass *
319 const TargetRegisterClass *
322 const TargetRegisterClass *
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| H A D | SIRegisterInfo.cpp | 435 const TargetRegisterClass *
930 const TargetRegisterClass *
2443 const TargetRegisterClass *
2503 const TargetRegisterClass *
2561 const TargetRegisterClass *
2572 const TargetRegisterClass *
2602 const TargetRegisterClass *
2681 const TargetRegisterClass *
2689 const TargetRegisterClass *
2697 const TargetRegisterClass *
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 45 class TargetRegisterClass {
342 const TargetRegisterClass *
598 virtual const TargetRegisterClass *
623 virtual const TargetRegisterClass *
723 const TargetRegisterClass*
762 const TargetRegisterClass *
769 virtual const TargetRegisterClass *
778 virtual const TargetRegisterClass *
787 virtual const TargetRegisterClass *
817 const TargetRegisterClass *RC) const = 0;
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| H A D | RegisterClassInfo.h | 76 void compute(const TargetRegisterClass *RC) const;
79 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
95 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
102 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
112 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
128 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
136 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
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| H A D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
136 BitVector getRegsAvailable(const TargetRegisterClass *RC);
140 Register FindUnusedReg(const TargetRegisterClass *RC) const;
172 Register scavengeRegister(const TargetRegisterClass *RC,
175 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
189 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
234 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
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| H A D | LiveStacks.h | 32 class TargetRegisterClass; variable
47 std::map<int, const TargetRegisterClass *> S2RCMap;
66 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
84 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
86 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
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| H A D | RegAllocCommon.h | 16 class TargetRegisterClass; variable
20 const TargetRegisterClass &RC)> RegClassFilterFunc;
25 const TargetRegisterClass &) { in allocateAllRegClasses() argument
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| H A D | FastISel.h | 56 class TargetRegisterClass; variable
391 const TargetRegisterClass *RC);
396 const TargetRegisterClass *RC, unsigned Op0);
401 const TargetRegisterClass *RC, unsigned Op0,
407 const TargetRegisterClass *RC, unsigned Op0,
413 const TargetRegisterClass *RC, unsigned Op0,
419 const TargetRegisterClass *RC, unsigned Op0,
425 const TargetRegisterClass *RC,
431 const TargetRegisterClass *RC, unsigned Op0,
437 const TargetRegisterClass *RC, uint64_t Imm);
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 60 const TargetRegisterClass *
61 getMatchingSuperRegClass(const TargetRegisterClass *A,
62 const TargetRegisterClass *B,
65 const TargetRegisterClass *
66 getSubClassWithSubReg(const TargetRegisterClass *RC,
69 const TargetRegisterClass *
70 getLargestLegalSuperClass(const TargetRegisterClass *RC,
73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
80 const TargetRegisterClass *
87 const TargetRegisterClass *
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| H A D | X86RegisterInfo.cpp | 84 const TargetRegisterClass *
85 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg()
96 const TargetRegisterClass *
109 const TargetRegisterClass *
125 const TargetRegisterClass *Super = RC; in getLargestLegalSuperClass()
126 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
176 const TargetRegisterClass *
232 const TargetRegisterClass *
246 const TargetRegisterClass *
258 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 194 const TargetRegisterClass *
211 const TargetRegisterClass *
218 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
229 const TargetRegisterClass *
236 const TargetRegisterClass *BestRC = nullptr; in getMinimalPhysRegClassLLT()
288 const TargetRegisterClass *
302 const TargetRegisterClass *
318 const TargetRegisterClass *TargetRegisterInfo::
336 const TargetRegisterClass *BestRC = nullptr; in getCommonSuperRegClass()
353 const TargetRegisterClass *RC = in getCommonSuperRegClass()
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| H A D | CriticalAntiDepBreaker.cpp | 71 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
89 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
119 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
126 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
196 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
206 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
321 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction()
330 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in ScanInstruction()
404 const TargetRegisterClass *RC, in findSuitableFreeRegister()
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| H A D | MachineRegisterInfo.cpp | 66 static const TargetRegisterClass *
68 const TargetRegisterClass *OldRC, in constrainRegClass()
72 const TargetRegisterClass *NewRC = in constrainRegClass()
82 const TargetRegisterClass *
103 else if (RegCB.is<const TargetRegisterClass *>() != in constrainRegAttrs()
104 ConstrainingRegCB.is<const TargetRegisterClass *>()) in constrainRegAttrs()
106 else if (RegCB.is<const TargetRegisterClass *>()) { in constrainRegAttrs()
108 *this, Reg, RegCB.get<const TargetRegisterClass *>(), in constrainRegAttrs()
122 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
123 const TargetRegisterClass *NewRC = in recomputeRegClass()
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| H A D | RegisterBank.cpp | 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| H A D | RegisterCoalescer.h | 22 class TargetRegisterClass; variable
57 const TargetRegisterClass *NewRC = nullptr;
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
62 const TargetRegisterClass *
63 getSubClassWithSubReg(const TargetRegisterClass *RC,
95 const TargetRegisterClass *
98 const TargetRegisterClass *
99 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
127 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
134 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
135 unsigned SubReg, const TargetRegisterClass *DstRC,
136 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.h | 60 const TargetRegisterClass *
69 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
101 const TargetRegisterClass *
102 getCrossCopyRegClass(const TargetRegisterClass *RC) const override { in getCrossCopyRegClass()
112 const TargetRegisterClass *intRegClass(unsigned Size) const;
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| H A D | M68kRegisterInfo.cpp | 70 const TargetRegisterClass *
77 const TargetRegisterClass *RC) const { in getMatchingMegaReg()
84 const TargetRegisterClass *
91 const TargetRegisterClass *BestRC = nullptr; in getMaximalPhysRegClass()
94 const TargetRegisterClass *RC = *I; in getMaximalPhysRegClass()
107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
266 const TargetRegisterClass *M68kRegisterInfo::intRegClass(unsigned size) const { in intRegClass()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 171 const TargetRegisterClass *
174 const TargetRegisterClass *
175 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
177 const TargetRegisterClass *
178 getLargestLegalSuperClass(const TargetRegisterClass *RC,
181 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
233 const TargetRegisterClass *SrcRC,
235 const TargetRegisterClass *DstRC,
237 const TargetRegisterClass *NewRC,
240 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
55 unsigned SubReg, const TargetRegisterClass *DstRC,
56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
69 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
73 const TargetRegisterClass *RC) const;
77 const TargetRegisterClass *
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| H A D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
123 const TargetRegisterClass *RC);
126 const TargetRegisterClass *RC);
131 const TargetRegisterClass *RC);
134 const TargetRegisterClass *RC);
146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 135 const TargetRegisterClass *
144 const TargetRegisterClass *
145 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
169 const TargetRegisterClass *SrcRC,
171 const TargetRegisterClass *DstRC,
173 const TargetRegisterClass *NewRC,
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | RegisterInfoEmitter-tsflags.td | 41 // CHECK: extern const TargetRegisterClass SDRegsRegClass = {
43 // CHECK: extern const TargetRegisterClass DRegsRegClass = {
45 // CHECK: extern const TargetRegisterClass MyRegsRegClass = {
47 // CHECK: extern const TargetRegisterClass SRegsRegClass = {
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