125     const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg);  in SGPRSpillBuilder()
199     const TargetRegisterClass &RC =  in prepare()
435 const TargetRegisterClass *
436 SIRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,  in getLargestLegalSuperClass()
922 const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(  in getPointerRegClass()
930 const TargetRegisterClass *
931 SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {  in getCrossCopyRegClass()
1290   const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);  in buildSpillLoadStore()
2181         const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass  in eliminateFrameIndex()
2242         const TargetRegisterClass *RC = IsSALU && !LiveSCC  in eliminateFrameIndex()
2395 static const TargetRegisterClass *
2419 static const TargetRegisterClass *
2443 const TargetRegisterClass *
2455 static const TargetRegisterClass *
2479 static const TargetRegisterClass *
2503 const TargetRegisterClass *
2513 static const TargetRegisterClass *
2537 static const TargetRegisterClass *
2561 const TargetRegisterClass *
2572 const TargetRegisterClass *
2602 const TargetRegisterClass *
2604   static const TargetRegisterClass *const BaseClasses[] = {  in getPhysRegClass()
2663   for (const TargetRegisterClass *BaseClass : BaseClasses) {  in getPhysRegClass()
2673   const TargetRegisterClass *RC;  in isSGPRReg()
2681 const TargetRegisterClass *
2682 SIRegisterInfo::getEquivalentVGPRClass(const TargetRegisterClass *SRC) const {  in getEquivalentVGPRClass()
2684   const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size);  in getEquivalentVGPRClass()
2689 const TargetRegisterClass *
2690 SIRegisterInfo::getEquivalentAGPRClass(const TargetRegisterClass *SRC) const {  in getEquivalentAGPRClass()
2692   const TargetRegisterClass *ARC = getAGPRClassForBitWidth(Size);  in getEquivalentAGPRClass()
2697 const TargetRegisterClass *
2698 SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const {  in getEquivalentSGPRClass()
2702   const TargetRegisterClass *SRC = getSGPRClassForBitWidth(Size);  in getEquivalentSGPRClass()
2707 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(  in getSubRegClass()
2708                          const TargetRegisterClass *RC, unsigned SubIdx) const {  in getSubRegClass()
2727 const TargetRegisterClass *
2728 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,  in getCompatibleSubRegClass()
2729                                          const TargetRegisterClass *SubRC,  in getCompatibleSubRegClass()
2732   const TargetRegisterClass *MatchRC =  in getCompatibleSubRegClass()
2747   const TargetRegisterClass *DefRC,  in shouldRewriteCopySrc()
2749   const TargetRegisterClass *SrcRC,  in shouldRewriteCopySrc()
2781                                               const TargetRegisterClass *RC,  in findUnusedRegister()
2796 ArrayRef<int16_t> SIRegisterInfo::getRegSplitParts(const TargetRegisterClass *RC,  in getRegSplitParts()
2811 const TargetRegisterClass*
2819   const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg);  in isVGPR()
2826   const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg);  in isAGPR()
2833                                     const TargetRegisterClass *SrcRC,  in shouldCoalesce()
2835                                     const TargetRegisterClass *DstRC,  in shouldCoalesce()
2837                                     const TargetRegisterClass *NewRC,  in shouldCoalesce()
2853 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,  in getRegPressureLimit()
2900 const TargetRegisterClass *
2919 const TargetRegisterClass *
2926   if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())  in getConstrainedRegClassForOperand()
2940 const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const {  in getVGPR64Class()
2946 const TargetRegisterClass *
3019   for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass,  in get32BitRegister()
3033 bool SIRegisterInfo::isProperlyAlignedRC(const TargetRegisterClass &RC) const {  in isProperlyAlignedRC()
3048 const TargetRegisterClass *
3049 SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {  in getProperlyAlignedRC()