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Searched refs:SysReg (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td43 let FilterClass = "SysReg";
77 def : SysReg<"uie", 0x004>;
78 def : SysReg<"utvec", 0x005>;
84 def : SysReg<"uepc", 0x041>;
88 def : SysReg<"uip", 0x044>;
125 def : SysReg<"sie", 0x104>;
146 def : SysReg<"sip", 0x144>;
173 def : SysReg<"hie", 0x604>;
182 def : SysReg<"hip", 0x644>;
249 def : SysReg<"mie", 0x304>;
[all …]
H A DRISCVInstrInfo.td1509 class ReadSysReg<SysReg SR, list<Register> Regs>
1517 class WriteSysReg<SysReg SR, list<Register> Regs>
1525 class WriteSysRegImm<SysReg SR, list<Register> Regs>
1533 class SwapSysReg<SysReg SR, list<Register> Regs>
1542 class SwapSysRegImm<SysReg SR, list<Register> Regs>
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp127 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); in printCSRSystemRegister() local
128 if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) in printCSRSystemRegister()
129 O << SysReg->Name; in printCSRSystemRegister()
H A DRISCVBaseInfo.h304 struct SysReg { struct
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dpseudo-inst-expansion.td14 class SysReg<bits<12> op> {
17 def SR : SysReg<0b111100001111>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp310 struct SysRegOp SysReg; member
333 SysReg = o.SysReg; in RISCVOperand()
789 return StringRef(SysReg.Data, SysReg.Length); in getSysReg()
871 Op->SysReg.Data = Str.data(); in createSysReg()
872 Op->SysReg.Length = Str.size(); in createSysReg()
873 Op->SysReg.Encoding = Encoding; in createSysReg()
1470 SysReg ? SysReg->Name : "", S, Imm, isRV64())); in parseCSRSystemRegister()
1485 if (!SysReg) in parseCSRSystemRegister()
1487 if (!SysReg) in parseCSRSystemRegister()
1490 SysReg->Name + "'"); in parseCSRSystemRegister()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp481 struct SysRegOp SysReg; member
536 SysReg = o.SysReg; in AArch64Operand()
666 return StringRef(SysReg.Data, SysReg.Length); in getSysReg()
1112 return SysReg.MRSReg != -1U; in isMRSSystemRegister()
1117 return SysReg.MSRReg != -1U; in isMSRSystemRegister()
2137 Op->SysReg.Data = Str.data(); in CreateSysReg()
2139 Op->SysReg.MRSReg = MRSReg; in CreateSysReg()
2140 Op->SysReg.MSRReg = MSRReg; in CreateSysReg()
3603 if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) { in tryParseSysReg()
3604 MRSReg = SysReg->Readable ? SysReg->Encoding : -1; in tryParseSysReg()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h629 struct SysReg { struct
646 const SysReg *lookupSysRegByName(StringRef); argument
647 const SysReg *lookupSysRegByEncoding(uint16_t);
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp1142 auto SysReg = AArch64SysReg::TPIDR_EL0; in expandMI() local
1145 SysReg = AArch64SysReg::TPIDR_EL3; in expandMI()
1147 SysReg = AArch64SysReg::TPIDR_EL2; in expandMI()
1149 SysReg = AArch64SysReg::TPIDR_EL1; in expandMI()
1151 .addImm(SysReg); in expandMI()
H A DAArch64SystemOperands.td583 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
603 : SysReg<name, op0, op1, crn, crm, op2> {
610 : SysReg<name, op0, op1, crn, crm, op2> {
617 : SysReg<name, op0, op1, crn, crm, op2> {
H A DAArch64InstrInfo.cpp1871 const AArch64SysReg::SysReg *SrcReg = in expandPostRAPseudo()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1543 static bool isValidSysReg(const AArch64SysReg::SysReg *Reg, bool Read, in isValidSysReg()
1555 static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read, in lookupSysReg()
1557 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); in lookupSysReg()
1584 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI); in printMRSSystemRegister()
1611 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI); in printMSRSystemRegister()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td2818 class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg,
2827 let Inst{22} = SysReg{3};
2831 let Inst{15-13} = SysReg{2-0};
2840 multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg,
2843 vfp_vstrldr<opc, 1, 0, SysReg, sysreg,
2850 vfp_vstrldr<opc, 1, 1, SysReg, sysreg,
2858 vfp_vstrldr<opc, 0, 1, SysReg, sysreg,
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp7356 StringRef SysReg = "") { in EmitSpecialRegisterBuiltin() argument
7365 if (SysReg.empty()) { in EmitSpecialRegisterBuiltin()
7367 SysReg = cast<clang::StringLiteral>(SysRegStrExpr)->getString(); in EmitSpecialRegisterBuiltin()
7370 llvm::Metadata *Ops[] = { llvm::MDString::get(Context, SysReg) }; in EmitSpecialRegisterBuiltin()
9913 unsigned SysReg = in EmitAArch64BuiltinExpr() local
9918 ((1 << 1) | ((SysReg >> 14) & 1)) << ":" << in EmitAArch64BuiltinExpr()
9919 ((SysReg >> 11) & 7) << ":" << in EmitAArch64BuiltinExpr()
9920 ((SysReg >> 7) & 15) << ":" << in EmitAArch64BuiltinExpr()
9921 ((SysReg >> 3) & 15) << ":" << in EmitAArch64BuiltinExpr()
9922 ( SysReg & 7); in EmitAArch64BuiltinExpr()