| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1115 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1116 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1254 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1256 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1305 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
1352 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1408 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
1471 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferStorePair()
1522 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeFlatLoadPair()
1570 Register SrcReg = MRI->createVirtualRegister(SuperRC); in mergeFlatStorePair()
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| H A D | SIRegisterInfo.h | 261 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.h | 71 const TargetRegisterClass *SuperRC,
77 const TargetRegisterClass *SuperRC,
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| H A D | SIRegisterInfo.cpp | 2728 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
2733 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
2734 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
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| H A D | SIInstrInfo.cpp | 4880 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
4898 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
4913 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
4925 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
4954 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
4955 if (!SuperRC) in isLegalRegOperand()
4958 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
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| H A D | AMDGPUISelDAGToDAG.cpp | 391 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
396 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 2659 const TargetRegisterClass *SuperRC, in computeIndirectRegIndex() argument
2673 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
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| H A D | SIISelLowering.cpp | 3727 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
3730 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 615 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
618 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
626 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
628 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
721 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
722 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| H A D | RegAllocGreedy.cpp | 1217 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1220 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1223 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1257 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1260 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1269 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
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| H A D | TargetLoweringBase.cpp | 1264 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1266 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1268 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1270 BestRC = SuperRC; in findRepresentativeClass()
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| H A D | MachineVerifier.cpp | 2143 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2145 if (!SuperRC) { in visitMachineOperand()
2149 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 583 const TargetRegisterClass *SuperRC = nullptr; in combine() local
585 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
589 SuperRC = &Hexagon::HvxWRRegClass; in combine()
595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| H A D | HexagonRegisterInfo.cpp | 438 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
439 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 409 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
410 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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