| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 206 unsigned SubReg0; in isProfitableToTransform() local
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
342 SubReg0 = 0; in transformInstruction()
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
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| H A D | AArch64ISelLowering.cpp | 20143 SDValue SubReg0 = DAG.getTargetConstant(AArch64::sube64, dl, MVT::i32); in createGPRPairNode() local
20145 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 376 SDValue SubReg0 = CurDAG->getTargetConstant(CSKY::sub32_0, dl, MVT::i32); in createGPRPairNode() local
378 const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1}; in createGPRPairNode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 185 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl() local
208 SubReg0 = SubReg2; in commuteInstructionImpl()
213 SubReg0 = SubReg1; in commuteInstructionImpl()
227 CommutedMI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1844 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1855 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode() local
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1866 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode() local
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1877 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode() local
1879 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1893 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
1908 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode()
[all …]
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| H A D | ARMISelLowering.cpp | 10248 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode() local
10250 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 208 unsigned SubReg0; in createTuple() local
218 SubReg0 = RISCV::sub_vrm1_0; in createTuple()
224 SubReg0 = RISCV::sub_vrm2_0; in createTuple()
230 SubReg0 = RISCV::sub_vrm4_0; in createTuple()
242 Ops.push_back(CurDAG.getTargetConstant(SubReg0 + I, DL, MVT::i32)); in createTuple()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 586 SDValue RC, SubReg0, SubReg1; in Select() local
590 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); in Select()
594 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
599 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, in Select()
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