| /llvm-project-15.0.7/clang/test/SemaTemplate/ |
| H A D | instantiate-subscript.cpp | 4 struct Sub0 { struct
24 template struct Subscript0<Sub0, int, int&>;
26 template struct Subscript0<Sub1, Sub0, long&>; // expected-note{{instantiation}}
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 242 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm() local
246 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 208 SDValue Sub0 = in selectInlineAsm() local
213 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 840 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64() local
844 DL, MVT::i32, LHS, Sub0); in SelectADD_SUB_I64()
849 DL, MVT::i32, RHS, Sub0); in SelectADD_SUB_I64()
882 Sub0, in SelectADD_SUB_I64()
1040 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32); in SelectMUL_LOHI() local
1042 MVT::i32, SDValue(Mad, 0), Sub0); in SelectMUL_LOHI()
1586 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectFlatOffsetImpl() local
1590 DL, MVT::i32, N0, Sub0); in SelectFlatOffsetImpl()
1609 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 433 const MCInst *Sub0 = MI.getOperand(0).getInst(); in EncodeSingleInstruction() local
437 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI); in EncodeSingleInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2234 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD() local
2237 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2518 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane() local
2521 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
5821 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm() local
5825 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 21324 SDValue Sub0 = getSubVectorSrc(Bop0, Index, SubVT); in narrowInsertExtractVectorBinOp() local
21330 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
21336 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, in narrowInsertExtractVectorBinOp()
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