| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | FrameAnalysis.cpp | 129 FIE.StackPtrReg, StackOffset, FIE.Size, FIE.IsSimple, IsIndexed)) { in decodeFrameAccess()
147 if (FIE.StackPtrReg == BC.MIB->getStackPointer() && SPOffset != SPT.EMPTY && in decodeFrameAccess()
152 } else if (FIE.StackPtrReg == BC.MIB->getFramePointer() && in decodeFrameAccess()
157 } else if (FIE.StackPtrReg == in decodeFrameAccess()
164 << "\n\tStack access reg: " << FIE.StackPtrReg << "\n"); in decodeFrameAccess()
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| H A D | ValidateInternalCalls.cpp | 238 FIE.StackPtrReg, StackOffset, FIE.Size, in analyzeFunction()
246 if (!FIE.IsLoad || FIE.StackPtrReg != BC.MIB->getStackPointer() || in analyzeFunction()
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| H A D | ShrinkWrapping.cpp | 521 if (FIE->StackPtrReg == BC.MIB->getStackPointer() && Slot < RegionAddr) in collapseRegion()
524 if (FIE->StackPtrReg == BC.MIB->getFramePointer() && Slot > RegionAddr) in collapseRegion()
612 if (FIE->StackPtrReg == BC.MIB->getStackPointer() && Slot < RegionAddr) in insertRegion()
614 if (FIE->StackPtrReg == BC.MIB->getFramePointer() && Slot >= RegionAddr) in insertRegion()
673 MCPhysReg StackPtrReg = 0; in performChanges() local
683 Reg, SrcImm, StackPtrReg, StackOffset, in performChanges()
692 if (StackPtrReg != BC.MIB->getFramePointer()) in performChanges()
696 Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size); in performChanges()
699 Inst, StackPtrReg, StackOffset + Adjustment, Reg, Size); in performChanges()
1549 MCPhysReg StackPtrReg = 0; in insertUpdatedCFI() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 758 Register StackPtrReg = FuncInfo->getStackPtrOffsetReg(); in emitPrologue() local
906 .addReg(StackPtrReg) in emitPrologue()
917 .addReg(StackPtrReg) in emitPrologue()
927 .addReg(StackPtrReg) in emitPrologue()
932 auto Add = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_I32), StackPtrReg) in emitPrologue()
933 .addReg(StackPtrReg) in emitPrologue()
978 const Register StackPtrReg = FuncInfo->getStackPtrOffsetReg(); in emitEpilogue() local
987 auto Add = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_I32), StackPtrReg) in emitEpilogue()
988 .addReg(StackPtrReg) in emitEpilogue()
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| H A D | SIRegisterInfo.cpp | 631 MCRegister StackPtrReg = MFI->getStackPtrOffsetReg(); in getReservedRegs() local
632 if (StackPtrReg) { in getReservedRegs()
633 reserveRegisterTuples(Reserved, StackPtrReg); in getReservedRegs()
634 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg)); in getReservedRegs()
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| /llvm-project-15.0.7/bolt/include/bolt/Passes/ |
| H A D | FrameAnalysis.h | 44 uint16_t StackPtrReg; member
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| /llvm-project-15.0.7/bolt/lib/Target/X86/ |
| H A D | X86MCPlusBuilder.cpp | 1038 uint16_t &StackPtrReg, int64_t &StackOffset, uint8_t &Size, in isStackAccess() argument
1045 StackPtrReg = X86::RSP; in isStackAccess()
1067 StackPtrReg = X86::RSP; in isStackAccess()
1138 StackPtrReg = BaseRegNum; in isStackAccess()
1886 uint16_t StackPtrReg; in convertMoveToConditionalMove() local
1891 StackPtrReg, StackOffset, Size, IsSimple, IsIndexed); in convertMoveToConditionalMove()
1897 RegInfo->isSubRegisterEq(X86::RBP, StackPtrReg)) in convertMoveToConditionalMove()
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| /llvm-project-15.0.7/bolt/include/bolt/Core/ |
| H A D | MCPlusBuilder.h | 899 int32_t &SrcImm, uint16_t &StackPtrReg, in isStackAccess() argument
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 5510 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in buildCallOperands() local
5512 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
7508 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); in LowerCall_AIX() local
7516 SDValue StackPtr = DAG.getRegister(StackPtrReg, PtrVT); in LowerCall_AIX()
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