| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 364 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
1074 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
1077 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
1080 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
1083 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
1087 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
1090 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1250 def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>;
1251 def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>;
1252 def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>;
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 66 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
67 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt()
68 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt()
70 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt()
2156 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
2157 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
2166 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
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| H A D | SIISelLowering.cpp | 10737 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
10739 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
10741 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 455 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
457 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
476 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
477 Srl.getOperand(0), in PreprocessISelDAG()
478 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
481 Srl, in PreprocessISelDAG()
482 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
484 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1923 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
1924 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract()
1934 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6146 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
6152 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); in lowerFPTOSI()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8118 SDValue Srl = DAG.getNode(ISD::SRL, DL, MVT::i64, Op0, Op1); in performANDCombine() local
8119 SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Srl, in performANDCombine()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4411 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
4412 AddToWorklist(Srl.getNode()); in visitSDIVLike()
4413 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike()
|