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Searched refs:SrcRC (Results 1 – 25 of 46) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr in copyPhysReg()
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp166 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
173 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
245 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
248 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
277 assert(TRI->isSGPRClass(SrcRC) && in foldVGPRCopyIntoRegSequence()
280 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
604 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
903 const TargetRegisterClass *SrcRC, *DstRC; in lowerSpecialCase() local
907 if (!isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) in lowerSpecialCase()
1136 SrcRC = TRI->getSubRegClass(SrcRC, SubReg); in lowerVGPR2SGPRCopies()
[all …]
H A DAMDGPUInstructionSelector.cpp110 const TargetRegisterClass *SrcRC in constrainCopyLikeIntrin() local
112 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
507 if (!SrcRC) in selectG_EXTRACT()
511 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg); in selectG_EXTRACT()
512 if (!SrcRC) in selectG_EXTRACT()
553 if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI)) in selectG_MERGE_VALUES()
582 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectG_UNMERGE_VALUES()
595 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
596 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectG_UNMERGE_VALUES()
1948 if (!SrcRC || !DstRC) in selectG_TRUNC()
[all …]
H A DSIRegisterInfo.h267 const TargetRegisterClass *SrcRC,
302 const TargetRegisterClass *SrcRC,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp254 if (SrcRC != DstRC) { in selectCopy()
290 if (DstRC != SrcRC) { in selectCopy()
690 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
733 if (!DstRC || !SrcRC) in selectTruncOrPtrToInt()
739 if (canTurnIntoCOPY(DstRC, SrcRC)) in selectTruncOrPtrToInt()
746 if (DstRC == SrcRC) { in selectTruncOrPtrToInt()
759 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in selectTruncOrPtrToInt()
865 if (canTurnIntoCOPY(SrcRC, DstRC)) in selectAnyext()
878 if (SrcRC == DstRC) { in selectAnyext()
888 .addImm(getSubRegIndex(SrcRC)); in selectAnyext()
[all …]
H A DX86DomainReassignment.cpp67 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC, in getDstRC() argument
70 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
72 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
74 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
76 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86RegisterInfo.h75 const TargetRegisterClass *SrcRC,
H A DX86InstrMMX.td123 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
134 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
138 (ins DstRC:$src1, SrcRC:$src2), asm,
139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp385 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
388 if (DefRC == SrcRC) in shareSameRegisterFile()
394 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
402 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
407 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
410 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
415 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
418 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
H A DDetectDeadLanes.cpp152 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
153 if (DstRC == SrcRC) in isCrossCopy()
178 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
181 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
183 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
184 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
H A DMachineCombiner.cpp177 auto SrcRC = MRI->getRegClass(Src); in isTransientMI() local
179 return TRI->getMatchingSuperRegClass(SrcRC, DstRC, SrcSub) != nullptr; in isTransientMI()
186 auto SrcRC = MRI->getRegClass(Src); in isTransientMI() local
188 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrInfo.td661 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
673 dag InOperandList = (ins SrcRC:$rt);
697 dag InOperandList = (ins SrcRC:$rt);
719 dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
728 RegisterOperand SrcRC,
731 dag InOperandList = (ins SrcRC:$fs);
741 dag InOperandList = (ins SrcRC:$impl);
814 dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
888 dag InOperandList = (ins SrcRC:$fs);
924 dag InOperandList = (ins SrcRC:$fs);
[all …]
H A DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
171 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
176 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h233 const TargetRegisterClass *SrcRC,
242 const TargetRegisterClass *SrcRC,
H A DARMBaseRegisterInfo.cpp878 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
893 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
899 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
938 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
942 SrcRC == &ARM::DPRRegClass && in shouldRewriteCopySrc()
947 SrcRC, SrcSubReg); in shouldRewriteCopySrc()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
H A DAVRRegisterInfo.cpp294 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
301 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, in shouldCoalesce()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
H A DHexagonRegisterInfo.cpp348 const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
359 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp234 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction() local
236 if (SrcRC == DstRC) { in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp380 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
397 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
H A DSystemZRegisterInfo.h169 const TargetRegisterClass *SrcRC,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h134 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp378 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
381 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
386 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()

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