110   const TargetRegisterClass *SrcRC  in constrainCopyLikeIntrin()  local
112   if (!DstRC || DstRC != SrcRC)  in constrainCopyLikeIntrin()
116          RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);  in constrainCopyLikeIntrin()
143       const TargetRegisterClass *SrcRC  in selectCOPY()  local
154         Register MaskedReg = MRI->createVirtualRegister(SrcRC);  in selectCOPY()
161             TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;  in selectCOPY()
171         MRI->setRegClass(SrcReg, SrcRC);  in selectCOPY()
505   const TargetRegisterClass *SrcRC =  in selectG_EXTRACT()  local
507   if (!SrcRC)  in selectG_EXTRACT()
511   SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg);  in selectG_EXTRACT()
512   if (!SrcRC)  in selectG_EXTRACT()
516                                     *SrcRC, I.getOperand(1));  in selectG_EXTRACT()
551     const TargetRegisterClass *SrcRC  in selectG_MERGE_VALUES()  local
553     if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))  in selectG_MERGE_VALUES()
580   const TargetRegisterClass *SrcRC =  in selectG_UNMERGE_VALUES()  local
582   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
588   ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);  in selectG_UNMERGE_VALUES()
595     SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);  in selectG_UNMERGE_VALUES()
596     if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))  in selectG_UNMERGE_VALUES()
1944   const TargetRegisterClass *SrcRC =  in selectG_TRUNC()  local
1948   if (!SrcRC || !DstRC)  in selectG_TRUNC()
1951   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_TRUNC()
2024       = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx);  in selectG_TRUNC()
2028     if (SrcWithSubRC != SrcRC) {  in selectG_TRUNC()
2085     const TargetRegisterClass *SrcRC =  in selectG_SZA_EXT()  local
2091     Register UndefReg = MRI->createVirtualRegister(SrcRC);  in selectG_SZA_EXT()
2101            RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI);  in selectG_SZA_EXT()
2129     const TargetRegisterClass &SrcRC = InReg && DstSize > 32 ?  in selectG_SZA_EXT()  local
2131     if (!RBI.constrainGenericRegister(SrcReg, SrcRC, *MRI))  in selectG_SZA_EXT()
2585   const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB);  in selectG_PTRMASK()  local
2590       !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_PTRMASK()
2700   const TargetRegisterClass *SrcRC =  in selectG_EXTRACT_VECTOR_ELT()  local
2704   if (!SrcRC || !DstRC)  in selectG_EXTRACT_VECTOR_ELT()
2706   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||  in selectG_EXTRACT_VECTOR_ELT()
2716   std::tie(IdxReg, SubReg) = computeIndirectRegIndex(*MRI, TRI, SrcRC, IdxReg,  in selectG_EXTRACT_VECTOR_ELT()
2748       TII.getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*SrcRC), true);  in selectG_EXTRACT_VECTOR_ELT()