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Searched refs:SrcMask (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1536 LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit); in computeSubRegLaneMasks() local
1539 assert(Idx2.LaneMask == SrcMask); in computeSubRegLaneMasks()
1556 I.Mask |= SrcMask; in computeSubRegLaneMasks()
1557 SrcMask = LaneBitmask::getNone(); in computeSubRegLaneMasks()
1560 if (SrcMask.any()) { in computeSubRegLaneMasks()
1561 MaskRolPair MaskRol = { SrcMask, RotateLeft }; in computeSubRegLaneMasks()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterCoalescer.cpp1628 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx); in eliminateUndefCopy() local
1630 if ((SR.LaneMask & SrcMask).none()) in eliminateUndefCopy()
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp7964 VPValue *SrcMask = createBlockInMask(Src, Plan); in createEdgeMask() local
7971 return EdgeMaskCache[Edge] = SrcMask; in createEdgeMask()
7977 return EdgeMaskCache[Edge] = SrcMask; in createEdgeMask()
7985 if (SrcMask) { // Otherwise block in-mask is all-one, no need to AND. in createEdgeMask()
7993 Builder.createSelect(SrcMask, EdgeMask, False, BI->getDebugLoc()); in createEdgeMask()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23388 SmallVectorImpl<APInt> *SrcMask = nullptr) { in matchScalarReduction() argument
23440 if (SrcMask) { in matchScalarReduction()
23443 SrcMask->push_back(SrcOpMap[SrcOp]); in matchScalarReduction()
49692 SmallVector<int, 16> SrcMask, ScaledMask; in isHorizontalBinOp() local
49694 if (getTargetShuffleInputs(BC, SrcOps, SrcMask, DAG) && in isHorizontalBinOp()
49695 !isAnyZero(SrcMask) && all_of(SrcOps, [BC](SDValue Op) { in isHorizontalBinOp()
49698 resolveTargetShuffleInputsAndMask(SrcOps, SrcMask); in isHorizontalBinOp()
49700 scaleShuffleElements(SrcMask, NumElts, ScaledMask)) { in isHorizontalBinOp()
49706 scaleShuffleElements(SrcMask, 2 * NumElts, ScaledMask)) { in isHorizontalBinOp()