Searched refs:SrcLo (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local 59 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg() 65 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg() 68 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local 753 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 921 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg() local 923 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo)); in copyPhysReg() 927 .addReg(SrcLo, KillFlag | UndefLo); in copyPhysReg() 1133 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo() local 1136 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); in expandPostRAPseudo() 1141 .addReg(SrcLo, Kill | UndefLo); in expandPostRAPseudo() 1403 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local 1409 .addReg(SrcLo); in expandPostRAPseudo() 1415 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local 1421 .addReg(SrcLo); in expandPostRAPseudo()
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| H A D | HexagonFrameLowering.cpp | 1935 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local 1951 if (LPR.contains(SrcLo)) { in expandStoreVec2() 1957 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2626 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT() local 2629 GetSplitVector(N->getOperand(0), SrcLo, SrcHi); in SplitVecRes_FP_TO_XINT_SAT() 2631 std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_FP_TO_XINT_SAT() 2633 Lo = DAG.getNode(N->getOpcode(), dl, DstVTLo, SrcLo, N->getOperand(1)); in SplitVecRes_FP_TO_XINT_SAT()
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