Searched refs:SrcHi (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 56 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
59 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
61 if (DestLo == SrcHi) { in copyPhysReg()
63 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
70 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 922 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() local
924 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); in copyPhysReg()
926 .addReg(SrcHi, KillFlag | UndefHi) in copyPhysReg()
1134 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo() local
1137 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); in expandPostRAPseudo()
1140 .addReg(SrcHi, UndefHi) in expandPostRAPseudo()
1404 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1408 .addReg(SrcHi) in expandPostRAPseudo()
1416 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1420 .addReg(SrcHi) in expandPostRAPseudo()
|
| H A D | HexagonFrameLowering.cpp | 1936 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
1962 if (LPR.contains(SrcHi)) { in expandStoreVec2()
1968 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2626 SDValue SrcLo, SrcHi; in SplitVecRes_FP_TO_XINT_SAT() local
2629 GetSplitVector(N->getOperand(0), SrcLo, SrcHi); in SplitVecRes_FP_TO_XINT_SAT()
2631 std::tie(SrcLo, SrcHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_FP_TO_XINT_SAT()
2634 Hi = DAG.getNode(N->getOpcode(), dl, DstVTHi, SrcHi, N->getOperand(1)); in SplitVecRes_FP_TO_XINT_SAT()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 7087 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
7089 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
|