Searched refs:SpillReg (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineFrameInfo.h | 67 void setDstReg(Register SpillReg) { in setDstReg() argument
68 DstReg = SpillReg; in setDstReg()
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| H A D | MachineInstrBuilder.h | 492 Register SpillReg);
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 129 Register SpillReg, int FI) { in buildPrologSpill() argument
138 LiveRegs.addReg(SpillReg); in buildPrologSpill()
139 TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, true, in buildPrologSpill()
142 LiveRegs.removeReg(SpillReg); in buildPrologSpill()
151 const DebugLoc &DL, Register SpillReg, int FI) { in buildEpilogRestore() argument
160 TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, false, in buildEpilogRestore()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 2164 Register SpillReg) { in computeExprForSpill() argument
2165 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI."); in computeExprForSpill()
2167 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg)) in computeExprForSpill()
2175 int FrameIndex, Register SpillReg) { in buildDbgValueForSpill() argument
2176 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg); in buildDbgValueForSpill()
2186 if (Op.isReg() && Op.getReg() == SpillReg) in buildDbgValueForSpill()
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