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Searched refs:SmallVT (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-shrink-v1i64.ll4 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp581 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
582 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
583 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
586 Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
587 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
588 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); in ShrinkDemandedOp()
H A DLegalizeIntegerTypes.cpp1504 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
1526 unsigned Shift = SmallVT.getScalarSizeInBits(); in PromoteIntRes_XMULO()
1536 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
H A DDAGCombiner.cpp9576 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
9577 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
9581 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
9584 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
9587 getShiftAmountTy(SmallVT))); in visitSRL()
21838 EVT SmallVT = V.getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
21839 if (!NVT.bitsEq(SmallVT)) in visitEXTRACT_SUBVECTOR()
21848 if (InsIdx * SmallVT.getScalarSizeInBits() == in visitEXTRACT_SUBVECTOR()
H A DSelectionDAGBuilder.cpp9232 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in lowerRangeToAssertZExt() local
9237 DAG.getValueType(SmallVT)); in lowerRangeToAssertZExt()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp4077 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
4086 DAG.getValueType(SmallVT)); in PerformDAGCombine()
4089 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
H A DSIISelLowering.cpp6771 EVT SmallVT = in lowerWorkitemID() local
6774 DAG.getValueType(SmallVT)); in lowerWorkitemID()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp713 for (auto SmallVT : SmallerVTs) { in RISCVTargetLowering() local
714 setTruncStoreAction(VT, SmallVT, Expand); in RISCVTargetLowering()
715 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand); in RISCVTargetLowering()