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Searched refs:Slot (Results 1 – 25 of 109) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DStackColoring.cpp604 int Slot = MO.getIndex(); in getStartOrEndSlot() local
605 if (Slot >= 0) in getStartOrEndSlot()
606 return Slot; in getStartOrEndSlot()
620 if (Slot < 0) in isLifetimeStartOrEnd()
624 slots.push_back(Slot); in isLifetimeStartOrEnd()
640 if (Slot<0) in isLifetimeStartOrEnd()
642 if (InterestingSlots.test(Slot) && applyFirstUse(Slot)) { in isLifetimeStartOrEnd()
693 if (Slot < 0) in collectMarkers()
720 if (Slot < 0) in collectMarkers()
943 VI.Slot = SlotRemap[VI.Slot]; in remapInstructions()
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H A DLiveStacks.cpp54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval() argument
55 assert(Slot >= 0 && "Spill slot indice must be >= 0"); in getOrCreateInterval()
56 SS2IntervalMap::iterator I = S2IMap.find(Slot); in getOrCreateInterval()
60 std::piecewise_construct, std::forward_as_tuple(Slot), in getOrCreateInterval()
61 std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F)) in getOrCreateInterval()
63 S2RCMap.insert(std::make_pair(Slot, RC)); in getOrCreateInterval()
66 const TargetRegisterClass *OldRC = S2RCMap[Slot]; in getOrCreateInterval()
67 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
78 int Slot = I->first; in print() local
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveStacks.h66 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
68 LiveInterval &getInterval(int Slot) { in getInterval() argument
69 assert(Slot >= 0 && "Spill slot indice must be >= 0"); in getInterval()
70 SS2IntervalMap::iterator I = S2IMap.find(Slot); in getInterval()
75 const LiveInterval &getInterval(int Slot) const { in getInterval() argument
76 assert(Slot >= 0 && "Spill slot indice must be >= 0"); in getInterval()
77 SS2IntervalMap::const_iterator I = S2IMap.find(Slot); in getInterval()
82 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() argument
84 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass() argument
85 assert(Slot >= 0 && "Spill slot indice must be >= 0"); in getIntervalRegClass()
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H A DRegisterScavenging.h81 for (ScavengedInfo &Slot : Scavenged) {
82 if (Slot.FrameIndex == FI) {
83 assert(!Slot.Reg || Slot.Reg == Reg);
84 Slot.Reg = Reg;
85 Slot.Restore = Restore;
H A DSlotIndexes.h85 enum Slot {
128 Slot getSlot() const {
129 return static_cast<Slot>(lie.getInt());
143 SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s)) {
269 Slot s = getSlot();
289 Slot s = getSlot();
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DDemoteRegToStack.cpp33 AllocaInst *Slot; in DemoteRegToStack() local
35 Slot = new AllocaInst(I.getType(), DL.getAllocaAddrSpace(), nullptr, in DemoteRegToStack()
38 Slot = new AllocaInst(I.getType(), DL.getAllocaAddrSpace(), nullptr, in DemoteRegToStack()
74 V = new LoadInst(I.getType(), Slot, I.getName() + ".reload", in DemoteRegToStack()
83 Value *V = new LoadInst(I.getType(), Slot, I.getName() + ".reload", in DemoteRegToStack()
102 new StoreInst(&I, Slot, &*InsertPt); in DemoteRegToStack()
103 return Slot; in DemoteRegToStack()
118 AllocaInst *Slot; in DemotePHIToStack() local
120 Slot = new AllocaInst(P->getType(), DL.getAllocaAddrSpace(), nullptr, in DemotePHIToStack()
135 new StoreInst(P->getIncomingValue(i), Slot, in DemotePHIToStack()
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/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DConstantMerge.cpp182 GlobalVariable *&Slot = CMap[Init]; in mergeConstants() local
187 bool FirstConstantFound = !Slot; in mergeConstants()
188 if (FirstConstantFound || IsBetterCanonical(GV, *Slot)) { in mergeConstants()
189 Slot = &GV; in mergeConstants()
214 GlobalVariable *Slot = Found->second; in mergeConstants() local
215 if (Slot == &GV) in mergeConstants()
218 if (makeMergeable(&GV, Slot) == CanMerge::No) in mergeConstants()
223 << Slot->getName() << "\n"); in mergeConstants()
224 SameContentReplacements.push_back(std::make_pair(&GV, Slot)); in mergeConstants()
H A DWholeProgramDevirt.cpp657 Constant *importGlobal(VTableSlot Slot, ArrayRef<uint64_t> Args,
1321 WholeProgramDevirtResolution *Res, VTableSlot Slot) { in tryICallBranchFunnel() argument
1343 if (isa<MDString>(Slot.TypeID)) { in tryICallBranchFunnel()
1514 std::string DevirtModule::getGlobalName(VTableSlot Slot, in getGlobalName() argument
1519 OS << cast<MDString>(Slot.TypeID)->getString() << '_' << Slot.ByteOffset; in getGlobalName()
1543 Slot, Args, Name, in exportConstant()
1567 Constant *C = importGlobal(Slot, Args, Name); in importConstant()
1617 VTableSlot Slot, ArrayRef<uint64_t> Args) { in tryUniqueRetValOpt() argument
1691 WholeProgramDevirtResolution *Res, VTableSlot Slot) { in tryVirtualConstProp() argument
2001 auto *TypeId = dyn_cast<MDString>(Slot.TypeID); in importResolution()
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/llvm-project-15.0.7/compiler-rt/lib/gwp_asan/tests/
H A Dcrash_handler_api.cpp29 size_t Slot = State.getNearestSlot(Addr); in metadata() local
31 Metadata[Slot].Addr = Addr; in metadata()
32 Metadata[Slot].RequestedSize = Size; in metadata()
33 Metadata[Slot].IsDeallocated = IsDeallocated; in metadata()
34 Metadata[Slot].AllocationTrace.ThreadID = 123; in metadata()
35 Metadata[Slot].DeallocationTrace.ThreadID = 321; in metadata()
36 setupBacktraces(&Metadata[Slot]); in metadata()
38 return Slot; in metadata()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp270 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
745 unsigned Opcode = (*Slot).getOpcode(); in searchRange()
782 RegDU.init(Slot); in searchBackward()
784 MachineBasicBlock::iterator SlotI = Slot; in searchBackward()
799 Iter Slot) const { in searchForward()
801 if (DisableForwardSearch || !Slot->isCall()) in searchForward()
808 RegDU.setCallerSaved(*Slot); in searchForward()
810 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) { in searchForward()
816 MBB.splice(std::next(Slot), &MBB, Filler); in searchForward()
817 MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); in searchForward()
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/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGExprAgg.cpp679 Slot.setExternallyDestructed(); in VisitCompoundLiteralExpr()
931 return CGF.EmitCallExpr(E, Slot); in VisitCallExpr()
1318 CGF.EmitCXXConstructExpr(E, Slot); in VisitCXXConstructExpr()
1387 AggValueSlot Slot = EnsureSlot(T); in VisitCXXScalarValueInitExpr() local
1393 AggValueSlot Slot = EnsureSlot(T); in VisitImplicitValueInitExpr() local
1952 if (Slot.isZeroed() || Slot.isVolatile() || !Slot.getAddress().isValid()) in CheckAggExprForMemSetUse()
1978 Address Loc = Slot.getAddress(); in CheckAggExprForMemSetUse()
1983 Slot.setZeroed(); in CheckAggExprForMemSetUse()
1996 assert((Slot.getAddress().isValid() || Slot.isIgnored()) && in EmitAggExpr()
2000 CheckAggExprForMemSetUse(Slot, E, *this); in EmitAggExpr()
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-regalloc-flags.ll26 ; DEFAULT-NEXT: Stack Slot Coloring
37 ; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis
54 ; BASIC-DEFAULT-NEXT: Stack Slot Coloring
66 ; DEFAULT-BASIC-NEXT: Stack Slot Coloring
71 ; BASIC-BASIC-NEXT: Live Stack Slot Analysis
84 ; BASIC-BASIC-NEXT: Stack Slot Coloring
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dstatepoint-stackmap-format.ll190 ; Indirect Spill Slot [RSP+0]
218 ; Indirect Spill Slot [RSP+16]
225 ; Indirect Spill Slot [RSP+8]
232 ; Indirect Spill Slot [RSP+16]
239 ; Indirect Spill Slot [RSP+16]
277 ; Indirect Spill Slot [RSP+0]
305 ; Indirect Spill Slot [RSP+16]
312 ; Indirect Spill Slot [RSP+8]
319 ; Indirect Spill Slot [RSP+16]
326 ; Indirect Spill Slot [RSP+16]
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp75 MachineBasicBlock::instr_iterator Slot,
144 MachineBasicBlock::instr_iterator Slot, in findDelayInstr() argument
149 insertDefsUses(Slot, RegDefs, RegUses); in findDelayInstr()
154 for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse(); in findDelayInstr()
/llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/Native/
H A DPDBStringTableBuilder.cpp187 uint32_t Slot = (Hash + I) % BucketCount; in writeHashTable() local
188 if (Buckets[Slot] != 0) in writeHashTable()
190 Buckets[Slot] = Offset; in writeHashTable()
/llvm-project-15.0.7/llvm/test/CodeGen/WinEH/
H A Dwineh-demotion.ll19 ; CHECK: [[Slot:%[^ ]+]] = alloca
27 ; CHECK-NEXT: store i32 %x, i32* [[Slot]]
33 ; CHECK-NEXT: store i32 %y, i32* [[Slot]]
46 ; CHECK: [[Reload:%[^ ]+]] = load i32, i32* [[Slot]]
125 ; CHECK: [[Slot:%[^ ]+]] = alloca
131 ; CHECK: store i32 %l, i32* [[Slot]]
139 ; CHECK: store i32 %r, i32* [[Slot]]
155 ; CHECK: store i32 %j, i32* [[Slot]]
168 ; CHECK: [[Reload:%[^ ]+]] = load i32, i32* [[Slot]]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.h87 SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
91 void AssignSlot(MachineInstr *MI, unsigned Slot);
H A DR600MachineScheduler.cpp348 void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) { in AssignSlot() argument
364 switch (Slot) { in AssignSlot()
380 SUnit *R600SchedStrategy::AttemptFillSlot(unsigned Slot, bool AnyAlu) { in AttemptFillSlot() argument
382 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
387 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DO3-pipeline.ll98 ; CHECK-NEXT: Slot index numbering
100 ; CHECK-NEXT: Local Stack Slot Allocation
128 ; CHECK-NEXT: Slot index numbering
137 ; CHECK-NEXT: Slot index numbering
150 ; CHECK-NEXT: Slot index numbering
159 ; CHECK-NEXT: Live Stack Slot Analysis
169 ; CHECK-NEXT: Stack Slot Coloring
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A DO3-pipeline.ll82 ; CHECK-NEXT: Slot index numbering
84 ; CHECK-NEXT: Local Stack Slot Allocation
99 ; CHECK-NEXT: Slot index numbering
119 ; CHECK-NEXT: Slot index numbering
126 ; CHECK-NEXT: Live Stack Slot Analysis
136 ; CHECK-NEXT: Stack Slot Coloring
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DDAGISelMatcher.h892 unsigned Slot; variable
895 : Matcher(EmitConvertToTarget), Slot(slot) {} in EmitConvertToTargetMatcher()
897 unsigned getSlot() const { return Slot; } in getSlot()
906 return cast<EmitConvertToTargetMatcher>(M)->Slot == Slot; in isEqualImpl()
970 unsigned Slot; variable
974 : Matcher(EmitNodeXForm), Slot(slot), NodeXForm(nodeXForm) {} in EmitNodeXFormMatcher()
976 unsigned getSlot() const { return Slot; } in getSlot()
986 return cast<EmitNodeXFormMatcher>(M)->Slot == Slot && in isEqualImpl()
/llvm-project-15.0.7/llvm/test/tools/llvm-dwp/X86/
H A Dincompatible_tu_index_version.s41 .long 2 # Slot count
65 .long 2 # Slot count
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A DO3-pipeline.ll82 ; CHECK-NEXT: Slot index numbering
84 ; CHECK-NEXT: Local Stack Slot Allocation
108 ; CHECK-NEXT: Slot index numbering
115 ; CHECK-NEXT: Live Stack Slot Analysis
125 ; CHECK-NEXT: Stack Slot Coloring
/llvm-project-15.0.7/compiler-rt/lib/gwp_asan/
H A Dcrash_handler.cpp57 size_t Slot = State->getNearestSlot(ErrorPtr); in __gwp_asan_diagnose_error() local
59 addrToMetadata(State, Metadata, State->slotToAddr(Slot)); in __gwp_asan_diagnose_error()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAsmWriter.cpp2427 int Slot; in WriteAsOperandInternal() local
2440 if (Slot == -1) in WriteAsOperandInternal()
2457 Slot = -1; in WriteAsOperandInternal()
2460 if (Slot != -1) in WriteAsOperandInternal()
2488 if (Slot == -1) { in WriteAsOperandInternal()
2497 Out << '!' << Slot; in WriteAsOperandInternal()
3273 assert(Slot != -1); in printVFuncId()
3274 Out << "^" << Slot; in printVFuncId()
3410 if (Slot == -1) in printNamedMDNode()
3834 Out << " %" << Slot; in printArgument()
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