| /llvm-project-15.0.7/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFExpression.h | 48 SignBit = 0x80, enumerator
49 SignedSize1 = SignBit | Size1,
50 SignedSize2 = SignBit | Size2,
51 SignedSize4 = SignBit | Size4,
52 SignedSize8 = SignBit | Size8,
53 SignedSizeLEB = SignBit | SizeLEB,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 336 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
340 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
345 SignBit = in SoftenFloatRes_FCOPYSIGN()
350 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
352 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
353 SignBit = in SoftenFloatRes_FCOPYSIGN()
2716 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftPromoteHalfRes_FCOPYSIGN()
2721 SignBit = in SoftPromoteHalfRes_FCOPYSIGN()
2726 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftPromoteHalfRes_FCOPYSIGN()
2728 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftPromoteHalfRes_FCOPYSIGN()
[all …]
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| H A D | LegalizeDAG.cpp | 71 uint8_t SignBit; member
1539 State.SignBit = NumBits - 1; in getSignAsIntValue()
1575 State.SignBit = 7; in getSignAsIntValue()
1613 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1627 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1629 if (SignBit.getScalarValueSizeInBits() < in ExpandFCOPYSIGN()
1631 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1636 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1639 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1641 if (SignBit.getScalarValueSizeInBits() > in ExpandFCOPYSIGN()
[all …]
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| H A D | DAGCombiner.cpp | 13704 SDValue SignBit = DAG.getConstant( in visitBITCAST() local
13708 FlipBit = SignBit; in visitBITCAST()
13717 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); in visitBITCAST()
13725 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); in visitBITCAST() local
13728 NewConv, DAG.getConstant(SignBit, DL, VT)); in visitBITCAST()
13731 NewConv, DAG.getConstant(~SignBit, DL, VT)); in visitBITCAST()
13773 APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2); in visitBITCAST() local
13787 DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); in visitBITCAST()
13794 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); in visitBITCAST() local
13796 X, DAG.getConstant(SignBit, SDLoc(X), VT)); in visitBITCAST()
[all …]
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| H A D | TargetLowering.cpp | 7679 APInt SignBit = APInt::getSignMask(BitSize); in expandIS_FPCLASS() local
7692 SDValue SignBitV = DAG.getConstant(SignBit, DL, IntVT); in expandIS_FPCLASS()
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| /llvm-project-15.0.7/flang/lib/Decimal/ |
| H A D | big-radix-floating-point.h | 349 constexpr Raw SignBit() const { return Raw{isNegative_} << (Real::bits - 1); } in RemoveLeastOrderZeroDigits() function
351 return (Raw{Real::maxExponent} << Real::significandBits) | SignBit(); in RemoveLeastOrderZeroDigits()
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| H A D | decimal-to-binary.cpp | 321 return {Real{SignBit()}}; in ConvertToBinary()
330 return {Real{SignBit()}, Inexact}; in ConvertToBinary()
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| /llvm-project-15.0.7/clang/lib/AST/Interp/ |
| H A D | Integral.h | 144 const T SignBit = T(1) << (TruncBits - 1);
146 return Integral((V & BitMask) | (Signed && (V & SignBit) ? ExtMask : 0));
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| /llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFExpression.cpp | 132 unsigned Signed = Size & Operation::SignBit; in extract()
137 switch (Size & ~Operation::SignBit) { in extract()
285 unsigned Signed = Size & Operation::SignBit; in print()
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| /llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/ |
| H A D | KnownBitsVectorTest.cpp | 620 auto SignBit = B.buildConstant(V2S32, 0x80000000); in TEST_F() local
638 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0))); in TEST_F()
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| H A D | KnownBitsTest.cpp | 707 auto SignBit = B.buildConstant(S32, 0x80000000); in TEST_F() local
713 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0))); in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1519 auto SignBit = B.buildShl(S64, ShiftOffset, ExtShift); in applyMappingBFE() local
1521 B.buildAShr(S64, SignBit, ExtShift); in applyMappingBFE()
1523 B.buildLShr(S64, SignBit, ExtShift); in applyMappingBFE()
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| H A D | AMDGPUISelLowering.cpp | 2087 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC() local
2090 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
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| H A D | AMDGPULegalizerInfo.cpp | 2160 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc() local
2167 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit}); in legalizeIntrinsicTrunc()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8877 APInt SignBit = APInt::getSignMask(32); in PerformDAGCombine() local
8880 DAG.getConstant(SignBit, DL, MVT::i32)); in PerformDAGCombine()
8885 DAG.getConstant(~SignBit, DL, MVT::i32)); in PerformDAGCombine()
9006 APInt SignBit = APInt::getSignMask(FPBits).sext(VT.getSizeInBits()); in PerformDAGCombine() local
9009 DAG.getConstant(SignBit, DL, VT)); in PerformDAGCombine()
9013 DAG.getConstant(~SignBit, DL, VT)); in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6041 auto SignBit = MIRBuilder.buildConstant(S64, 63); in lowerSITOFP() local
6042 auto S = MIRBuilder.buildAShr(S64, L, SignBit); in lowerSITOFP()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23293 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask); in LowerFCOPYSIGN() local
23311 SDValue Or = DAG.getNode(X86ISD::FOR, dl, LogicVT, MagBits, SignBit); in LowerFCOPYSIGN()
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