| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64Schedule.td | 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| H A D | AArch64SchedA55.td | 68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
223 // Shifted operand
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| H A D | AArch64SchedAmpere1.td | 591 } // ALU of Shifted-Reg
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| H A D | AArch64SchedA57.td | 144 // Shifted Register with Shift == 0
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| /llvm-project-15.0.7/polly/lib/Support/ |
| H A D | ISLTools.cpp | 231 isl::set Shifted = shiftDim(Set, Pos, Amount); in shiftDim() local
232 Result = Result.unite(Shifted); in shiftDim()
271 isl::map Shifted = shiftDim(Map, Dim, Pos, Amount); in shiftDim() local
272 Result = Result.unite(Shifted); in shiftDim()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | misched-fusion-arith-logic.mir | 75 ; Shifted register.
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| /llvm-project-15.0.7/clang/lib/Tooling/ASTDiff/ |
| H A D | ASTDiff.cpp | 150 int findPositionInParent(NodeId Id, bool Shifted = false) const;
339 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const { in findPositionInParent()
346 if (Shifted) in findPositionInParent()
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| /llvm-project-15.0.7/clang-tools-extra/clangd/refactor/ |
| H A D | Rename.cpp | 823 Position Shifted = { in buildRenameEdit() local
827 positionToOffset(InitialCode.substr(LastOffset), Shifted); in buildRenameEdit()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 1006 Value *Shifted = IC.Builder.CreateLShr(Masked, ShiftAmt); in instCombineIntrinsic() local
1007 return IC.replaceInstUsesWith(II, Shifted); in instCombineIntrinsic()
1049 Value *Shifted = IC.Builder.CreateShl(Input, ShiftAmt); in instCombineIntrinsic() local
1050 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic()
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| H A D | X86ISelLowering.cpp | 28606 SDValue Shifted = in LowerSET_ROUNDING() local
28609 RMBits = DAG.getNode(ISD::AND, DL, MVT::i16, Shifted, in LowerSET_ROUNDING()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2858 unsigned Shifted = 0; in alignToARMConstant() local
2865 Shifted += 2; in alignToARMConstant()
2874 if (Shifted > 24) in alignToARMConstant()
2875 Value = Value >> (Shifted - 24); in alignToARMConstant()
2877 Value = Value << (24 - Shifted); in alignToARMConstant()
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| H A D | ARMScheduleM7.td | 322 // Shifted ALU operands are read a cycle early.
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| H A D | ARMInstrThumb2.td | 54 // Shifted operands. No register controlled shifts for Thumb2.
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| /llvm-project-15.0.7/clang/lib/Format/ |
| H A D | Format.cpp | 3182 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, in fixCppIncludeInsertions() local
3184 Result = Result.merge(tooling::Replacements(Shifted)); in fixCppIncludeInsertions()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 5733 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
5734 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false); in createAddRecFromPHI()
5735 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
5743 insertValueToMap(PN, Shifted); in createAddRecFromPHI()
5744 return Shifted; in createAddRecFromPHI()
12919 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
12921 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3296 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); in lower() local
3297 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); in lower()
7212 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH() local
7213 MIRBuilder.buildTrunc(Result, Shifted); in lowerSMULH_UMULH()
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/ |
| H A D | neon-instructions.txt | 85 # Vector Move Immediate Shifted
86 # Vector Move Inverted Immediate Shifted
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 6408 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
6410 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6700 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerGET_ROUNDING() local
6702 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING()
6730 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerSET_ROUNDING() local
6732 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerSET_ROUNDING()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 589 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
7401 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
7413 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
7416 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13358 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub() local
13360 auto Final = Shifted; in generateEquivalentSub()
13364 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11382 SDValue Shifted = DAG.getZExtOrTrunc(Shift.getOperand(0), in performCvtF32UByteNCombine() local
11393 MVT::f32, Shifted); in performCvtF32UByteNCombine()
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