| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 872 ARM_AM::ShiftOpc ShiftTy; member
882 ARM_AM::ShiftOpc ShiftTy; member
889 ARM_AM::ShiftOpc ShiftTy; member
3835 Op->PostIdxReg.ShiftTy = ShiftTy; in CreatePostIdxReg()
4176 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
4203 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
4204 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
4211 ShiftTy = ARM_AM::lsl; in tryParseShiftRegister()
10131 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
10156 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 787 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
799 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
810 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
811 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
817 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
818 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 181 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2768 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 4755 EVT ShiftTy = in SimplifySetCC() local
4764 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC()
4782 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() local
4793 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
4821 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
9067 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointMul() local
9069 DAG.getConstant(Scale, dl, ShiftTy)); in expandFixedPointMul()
9097 DAG.getConstant(VTSize - 1, dl, ShiftTy)); in expandFixedPointMul()
9164 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointDiv() local
9167 DAG.getConstant(LHSShift, dl, ShiftTy)); in expandFixedPointDiv()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 3155 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
3160 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
3161 assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(Op1.getValueSizeInBits()) && in visitShift()
3163 Op2 = DAG.getZExtOrTrunc(Op2, getCurSDLoc(), ShiftTy); in visitShift()
5449 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local
5454 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
5458 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
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| H A D | LegalizeIntegerTypes.cpp | 4194 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
4195 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4196 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 4515 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local
4518 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost()
4814 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local
4817 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
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| H A D | X86ISelLowering.cpp | 48540 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
48541 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
48546 Shift.getConstantOperandAPInt(1) != (ShiftTy.getSizeInBits() - 1)) in foldXorTruncShiftIntoCmp()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1785 LLT ShiftTy = SrcTy; in widenScalarExtract() local
1788 ShiftTy = WideTy; in widenScalarExtract()
1792 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
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| H A D | CombinerHelper.cpp | 1615 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local
1616 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2988 const LLT ShiftTy = MRI.getType(ShiftReg); in select() local
2991 ShiftTy.getSizeInBits() == 64) { in select()
2992 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in select()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1517 …multiclass adrShiftPat<ValueType Ty, ValueType PredTy, ValueType ShiftTy, Instruction DestAdrIns, …
1521 (Ty (splat_vector (ShiftTy ShiftAmt)))))),
|