872     ARM_AM::ShiftOpc ShiftTy;  member
882     ARM_AM::ShiftOpc ShiftTy;  member
889     ARM_AM::ShiftOpc ShiftTy;  member
1459     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isPostIdxReg()
2562       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
2573       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
3314                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
3652     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
3665     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
3830   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3835     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
3973     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
3974       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
3996        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "  in print()
4001        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"  in print()
4150   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)  in tryParseShiftRegister()  local
4159   if (ShiftTy == ARM_AM::no_shift)  in tryParseShiftRegister()
4176   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
4203           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
4204           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
4211         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
4227   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
4228     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,  in tryParseShiftRegister()
4232     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
5664   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
5668     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
5675   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,  in parsePostIdxReg()
10131     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10134     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10135     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10136     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10137     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10139     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
10156     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10159     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10160     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10161     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10162     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10168     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
10170     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()