Searched refs:ShiftReg (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1503 Register ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1523 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1534 .addReg(ShiftReg) in EmitShiftInstr()
1535 .addReg(ShiftReg); in EmitShiftInstr()
1538 .addReg(ShiftReg); in EmitShiftInstr()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1678 Register ShiftReg = RI.createVirtualRegister(RC); in insertShift() local
1690 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); in insertShift()
1692 ShiftMI.addReg(ShiftReg); in insertShift()
1700 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 884 unsigned ShiftReg; member
1399 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2560 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3649 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3654 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3997 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4175 int ShiftReg = 0; in tryParseShiftRegister() local
4180 ShiftReg = SrcReg; in tryParseShiftRegister()
4215 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4216 if (ShiftReg == -1) { in tryParseShiftRegister()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2987 Register ShiftReg = I.getOperand(2).getReg(); in select() local
2988 const LLT ShiftTy = MRI.getType(ShiftReg); in select()
2995 .addReg(ShiftReg, 0, AArch64::sub_32); in select()
6547 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister() local
6549 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits(); in selectShiftedRegister()
6553 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11605 Register ShiftReg = in EmitPartwordAtomicBinary() local
11661 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
11686 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
11713 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
11755 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12612 Register ShiftReg = in EmitInstrWithCustomInserter() local
12676 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
12692 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
12695 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
12706 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
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